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AD5533ABC-1_

32-Channel, 14-Bit DAC with Precision Infinite Sample-and-Hold Mode

Analog Devices 

AD5532B

MICROPROCESSOR INTERFACING

AD5532B to ADSP-21xx Interface

The ADSP-21xx family of DSPs is easily interfaced to the

AD5532B without the need for extra logic.

A data transfer is initiated by writing a word to the TX register

after the SPORT has been enabled. In a write sequence, data is

clocked out on each rising edge of the DSP’s serial clock and

clocked into the AD5532B on the falling edge of its SCLK.

In readback, 16 bits of data are clocked out of the AD5532B on

each rising edge of SCLK and clocked into the DSP on the

rising edge of SCLK. DIN is ignored. The valid 14 bits of data

will be centered in the 16-bit RX register when using this configu-

ration. The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0, External Framing Signal

ITFS = 1, Internal Framing Signal

SLEN = 1001, 10-Bit Data-Words (ISHA Mode Write)

SLEN = 0111, 3 8-Bit Data-Words (DAC Mode Write)

SLEN = 1111, 16-Bit Data-Words (Readback Mode)

Figure 11 shows the connection diagram.

AD5532B*

DOUT

SYNC

DIN

SCLK

ADSP-2101/

DR ADSP-2103*

TFS

RFS

DT

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 11. AD5532B to ADSP-2101/ADSP-2103 Interface

AD5532B to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is confi-

gured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0,

and the clock phase bit (CPHA) = 1. The SPI is configured by

writing to the SPI control register (SPCR)—see 68HC11 User

Manual. SCK of the 68HC11 drives the SCLK of the AD5532B, the

MOSI output drives the serial data line (DIN) of the AD5532B,

and the MISO input is driven from DOUT. The SYNC signal is

derived from a port line (PC7). A connection diagram is shown

in Figure 12.

AD5532B*

DOUT

SYNC

SCLK

DIN

MC68HC11*

MISO

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 12. AD5532B to MC68HC11 Interface

When data is being transmitted to the AD5532B, the SYNC line

is taken low (PC7). Data appearing on the MOSI output is valid

on the falling edge of SCK. Serial data from the 68HC11 is

transmitted in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. Data is transmitted MSB first. In

order to transmit 10 data bits in ISHA mode, it is important to

left-justify the data in the SPDR register. PC7 must be pulled

low to start a transfer. It is taken high and pulled low again before

any further read/write cycles can take place.

AD5532B to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured as

an SPI master with the clock polarity bit = 0. This is done by

writing to the synchronous serial port control register (SSPCON).

See PIC16/17 Microcontroller User Manual. In this example,

I/O port RA1 is being used to pulse SYNC and enable the serial

port of the AD5532B. This microcontroller transfers only eight

bits of data during each serial transfer operation; therefore, two or

three consecutive read/write operations are needed depending

on the mode. Figure 13 shows the connection diagram.

AD5532B*

SCLK

DOUT

DIN

SYNC

PIC16C6x/7x*

SCK/RC3

SDO/RC5

SDI/RC4

RA1

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. AD5532B to PIC16C6x/7x Interface

AD5532B to 8051

The AD5532B requires a clock synchronized to the serial data. The

8051 serial interface must therefore be operated in Mode 0. In this

mode, serial data enters and exits through RxD and a shift clock

is output on TxD. Figure 14 shows how the 8051 is connected

to the AD5532B. Because the AD5532B shifts data out on the

rising edge of the shift clock and latches data in on the falling

edge, the shift clock must be inverted. The AD5532B requires its

data with the MSB first. Since the 8051 outputs the LSB first,

the transmit routine must take this into account.

AD5532B*

SCLK

DOUT

DIN

SYNC

8051*

TxD

RxD

P1.1

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 14. AD5532B to 8051 Interface

–14–

REV. A

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