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AD484M1644VTA-15 Ver la hoja de datos (PDF) - Unspecified

Número de pieza
componentes Descripción
Fabricante
AD484M1644VTA-15
ETC
Unspecified ETC
AD484M1644VTA-15 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Ascend Semiconductor Corporation 64Mb SDRAM
Current
state
Write recovering
Write recovering
with AP
Refreshing
Mode Register
Accessing
/CS /R /C /W Addr.
Command
HXXX
X
DESL
LHHH
X
NOP
LHH L
X
BST
L H L H BA/CA/A10 READ/READA
L H L L BA/CA/A10 WRIT/WRITA
L L H H BA/RA
ACT
L L H L BA, A10
PRE/PALL
LL LH
X
REF/SELF
L L L L Op-Code
MRS
HXXX
X
DESL
LHHH
X
NOP
LHH L
X
BST
L H L H BA/CA/A10 READ/READA
L H L L BA/CA/A10 WRIT/WRITA
L L H H BA/RA
ACT
L L H L BA, A10
PRE/PALL
LL LH
X
REF/SELF
L L L L Op-Code
MRS
HXXX
X
DESL
LHH X
X
NOP/ BST
LH L X
X
READ/WRIT
LLHX
X
ACT/PRE/PALL
LL L X
X
REF/SELF/MRS
HXXX
X
DESL
LHHH
X
NOP
LHH L
X
BST
LH L X
X
READ/WRIT
LL XX
X
ACT/PRE/PALL/
REF/SELF/MRS
Action
Nop Enter row active after tDPL
Nop Enter row active after tDPL
Nop Enter row active after tDPL
Start read, Determine AP
New write, Determine AP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop Enter precharge after tDPL
Nop Enter precharge after tDPL
Nop Enter precharge after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop Enter idle after tRC
Nop Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Nop
Nop
ILLEGAL
ILLEGAL
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
Notes
8
3
3
3,8
3
3
Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states;
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recov ery requirements.
9. Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Preliminary
13

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