AD5172BRM100(RevA) Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD5172BRM100
(Rev.:RevA)

256-Position One-Time Programmable Dual-Channel I2C Digital Potentiometers

Analog Devices 

AD5172/AD5173

TIMING CHARACTERISTICS—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 3. VDD = 5 V ± 10% or 3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted

Parameter

Symbol Conditions

I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications Apply to All Parts)

Min Typ Max Unit

SCL Clock Frequency

fSCL

tBUF Bus Free Time between STOP and START

t1

tHD;STA Hold Time (Repeated START)

t2

tLOW Low Period of SCL Clock

t3

tHIGH High Period of SCL Clock

t4

tSU;STA Setup Time for Repeated START Condition t5

tHD;DAT Data Hold Time2

t6

tSU;DAT Data Setup Time

t7

tF Fall Time of Both SDA and SCL Signals

t8

tR Rise Time of Both SDA and SCL Signals

t9

tSU;STO Setup Time for STOP Condition

t10

1.3

After this period, the first clock pulse is

0.6

generated.

1.3

0.6

0.6

100

0.6

400 kHz

µs

µs

µs

µs

µs

0.9 µs

ns

300 ns

300 ns

µs

1 See timing diagrams for locations of measured values.

2 The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

Rev. A | Page 5 of 24

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