AD5170BRM100-RL7(RevA) Ver la hoja de datos (PDF) - Analog Devices

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AD5170BRM100-RL7
(Rev.:RevA)

256-Position Two-Time Programmable I2C Digital Potentiometer

Analog Devices 

AD5170

TIMING CHARACTERISTICS — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter

Symbol Conditions

I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications apply to all parts)

SCL Clock Frequency

fSCL

tBUF Bus Free Time between STOP and START

t1

tHD;STA Hold Time (Repeated START)

t2

After this period, the first clock

pulse is generated.

tLOW Low Period of SCL Clock

t3

tHIGH High Period of SCL Clock

t4

tSU;STA Setup Time for Repeated START Condition

t5

tHD;DAT Data Hold Time2

t6

tSU;DAT Data Setup Time

t7

tF Fall Time of Both SDA and SCL Signals

t8

tR Rise Time of Both SDA and SCL Signals

t9

tSU;STO Setup Time for STOP Condition

t10

Min Typ Max Unit

400 kHz

1.3

µs

0.6

µs

1.3

µs

0.6

µs

0.6

µs

0.9 µs

100

ns

300 ns

300 ns

0.6

µs

1 See timing diagrams for locations of measured values.

2 The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

Rev. A | Page 5 of 24

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