A64S06161A Ver la hoja de datos (PDF) - AMIC Technology
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A64S06161A Datasheet PDF : 13 Pages
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Preliminary
A64S06161A
WRITE CYCLE 1 (/CS Controlled, /PD = VIH)
tWC
ADDR
/CS
/UB,/LB
/WE
tAS
tCW
tAW
tBW
tWP
Data In
High-Z
Data
Out
High-Z
tWR
tP
tDW
tDH
Data Valid
High-Z
WRITE CYCLE 2 (/UB /LB Controlled, /PD = VIH)
tWC
ADDR
/CS
/UB,/LB
/WE
tAS(3)
tCW(2)
tAW
tBW
tWP
Data In
tWR(4)
tP
tDW
tDH
Data Valid
Data
Out
High-Z
Notes (WRITE CYCLE) :
1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest
transition among /CS going low and /WE going low: A write end at the earliest
transition among /CS going high and /WE going high. tWP is measured from the
beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends
as /CS.
5. Do not access device with cycle timing shorter than tRC for continuous periods > 16us.
(March, 2005, Version 0.0)
10
AMIC Technology, Corp.
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