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A25L80P

8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface

AMIC Technology 

Figure 16. Release from Deep Power-down (RES) Instruction Sequence

S

tRES1

C

01 2 3 45 6 7

Instruction

D

High Impedance

Q

Deep Power-down Mode Stand-by Mode

A25L80P

Driving Chip Select ( S ) High after the 8-bit instruction byte has

been received by the device, but before the whole of the 8-bit

Electronic Signature has been transmitted for the first time (as

shown in Figure 16.), still insures that the device is put into

Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by Power

mode is immediate. If the device was previously in the Deep

Power-down mode, though, the transition to the Stand-by

Power mode is delayed by tRES1, and Chip Select ( S ) must

remain High for at least tRES1 (max), as specified in AC

Characteristics Table. Once in the Stand-by Power mode, the

device waits to be selected, so that it can receive, decode and

execute instructions.

PRELIMINARY (May 2005, Version 0.0)

21

AMIC Technology Corp.

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