A10V10BVQ80C Ver la hoja de datos (PDF) - Actel Corporation
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A10V10BVQ80C Datasheet PDF : 24 Pages
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ACT™ 1 Series FPGAs
ACT 1 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description
TTL Output Module Timing1
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tDLH
Data to Pad High
tDHL
Data to Pad Low
tENZH
Enable Pad Z to High
tENZL
Enable Pad Z to Low
tENHZ
Enable Pad High to Z
tENLZ
Enable Pad Low to Z
dTLH
Delta Low to High
dTHL
Delta High to Low
CMOS Output Module Timing1
6.7
7.6
8.7
10.3
15.0 ns
7.5
8.6
9.8
11.5
16.7 ns
6.6
7.5
8.6
10.2
14.8 ns
7.9
9.1
10.4
12.2
17.7 ns
10.0
11.6
13.1
15.4
22.4 ns
9.0
10.4
11.8
13.9
20.2 ns
0.06
0.07
0.08
0.09
0.13 ns/pF
0.08
0.09
0.10
0.12
0.17 ns/pF
tDLH
Data to Pad High
7.9
9.2
10.4
12.2
17.7 ns
tDHL
Data to Pad Low
6.4
7.2
8.2
9.8
14.2 ns
tENZH
Enable Pad Z to High
6.0
6.9
7.9
9.2
13.4 ns
tENZL
Enable Pad Z to Low
8.3
9.4
10.7
12.7
18.5 ns
tENHZ
Enable Pad High to Z
10.0
11.6
13.1
15.4
22.4 ns
tENLZ
Enable Pad Low to Z
9.0
10.4
11.8
13.9
20.2 ns
dTLH
Delta Low to High
0.10
0.11
0.13
0.15
0.22 ns/pF
dTHL
Delta High to Low
0.06
0.07
0.08
0.09
0.13 ns/pF
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125.
1-299
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