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A10V10BPQ80C Ver la hoja de datos (PDF) - Actel Corporation

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componentes Descripción
Fabricante
A10V10BPQ80C
ACTEL
Actel Corporation ACTEL
A10V10BPQ80C Datasheet PDF : 24 Pages
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ACT1 Series FPGAs
ACT 1 Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)1
Logic Module Propagation Delays
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
tPD1
Single Module
tPD2
Dual Module Macros
tCO
Sequential Clk to Q
tGO
Latch G to Q
tRS
Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
2.9
3.4
3.8
4.5
6.5 ns
6.8
7.8
8.8
10.4
15.1 ns
2.9
3.4
3.8
4.5
6.5 ns
2.9
3.4
3.8
4.5
6.5 ns
2.9
3.4
3.8
4.5
6.5 ns
tRD1
FO=1 Routing Delay
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
Sequential Timing Characteristics3
0.9
1.1
1.2
1.4
2.0 ns
1.4
1.7
1.9
2.2
3.2 ns
2.1
2.5
2.8
3.3
4.8 ns
3.1
3.6
4.1
4.8
7.0 ns
6.6
7.7
8.7
10.2
14.8 ns
tSUD
Flip-Flop (Latch) Data Input Setup 5.5
6.4
7.2
8.5
10.0
ns
tHD4
Flip-Flop (Latch) Data Input Hold 0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
5.5
6.4
7.2
8.5
10.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
6.8
8.0
9.0
10.5
9.8
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
6.8
8.0
9.0
10.5
9.8
ns
tA
fMAX
Flip-Flop Clock Input Period
Flip-Flop (Latch) Clock
Frequency (FO = 128)
14.2
16.7
18.9
22.3
20.0
ns
70
60
53
45
50 MHz
Notes:
1. VCC = 3.0 V for 3.3V specifications.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.
4. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro.
1-297

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