88E1111-XX-RCJ-C000 Ver la hoja de datos (PDF) - Marvell Semiconductor
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88E1111-XX-RCJ-C000 Datasheet PDF : 52 Pages
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88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 2: GMII/MII Interfaces (Continued)
117-TFBGA 96-BCC
Pin #
Pin #
C5
86
A2
87
A1
89
C4
90
B3
91
C3
93
D3
92
B2
95
128-PQFP Pin Name
Pin #
120
RXD[7]
121
RXD[6]
123
RXD[5]
124
RXD[4]
125
RXD[3]/RXD[3]
126
RXD[2]/RXD[2]
128
RXD[1]/RXD[1]
3
RXD[0]/RXD[0]
Pin
Ty p e
O, Z
B5
84
115
CRS
O, Z
B6
83
114
COL
O, Z
Description
GMII and MII Receive Data. Symbols
received on the cable are decoded and pre-
sented on RXD[7:0] in 1000BASE-T mode.
In MII mode, RXD[3:0] are used in
100BASE-TX and 10BASE-T modes. In MII
mode, RXD[7:4] are driven low.
RXD[7:0] is synchronous to RX_CLK.
GMII and MII Carrier Sense. CRS asserts
when the receive medium is non-idle. In half-
duplex mode, CRS is also asserted during
transmission. CRS assertion during half-
duplex transmit can be disabled by program-
ming register 16.11 to 0.
CRS is asynchronous to RX_CLK,
GTX_CLK, and TX_CLK.
GMII and MII Collision. In 10/100/
1000BASE-T full-duplex modes, COL is
always low. In 10/100/1000BASE-T half-
duplex modes, COL asserts only when both
the transmit and receive media are non-idle.
In 10BASE-T half-duplex mode, COL is
asserted to indicate signal quality error
(SQE). SQE can be disabled by clearing reg-
ister 16.2 to zero.
COL is asynchronous to RX_CLK,
GTX_CLK, and TX_CLK.
Doc. No. MV-S105540-00, Rev. --
Page 14
Document Classification: Proprietary Information
Copyright © 2009 Marvell
March 4, 2009, Advance
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