317697-001 Ver la hoja de datos (PDF) - Intel

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317697-001

Gigabit Ethernet Controller

Intel 

82575 Gigabit Ethernet Controller Datasheet

Tsu

Thold

Tval

Tor

Tof

Todr1

Todf1

Tidr2

Tidf2

Tir

Tif

7.4.4

Table 18.

REF_CLK Frequency

50

MHz

2

REF_CLK Duty Cycle

35

65

%

1

REF_CLK accuracy

100

ppm

TXD[1:0], TX_EN, Data Setup to REF_CLK

rising edge

3

ns

TXD[1:0], TX_EN Data hold from REF_CLK

rising edge

1.5

ns

6

RXD[1:0], CRS_DV Data valid from REF_CLK

rising edge

1.8

9

ns

RXD[1:0], CRS_DV Output Time rise

0.5

6

ns

3

RXD[1:0], CRS_DV Output Time fall

0.5

6

ns

3

RXD[1:0], CRS_DV Output delay rise

2

5.8

ns

3

RXD[1:0], CRS_DV Output delay fall

2

5.8

ns

3

TXD[1:0], TX_EN Input delay rise

0.5

6

ns

4, 5

TXD[1:0], TX_EN Input delay fall

0.5

6

ns

4, 5

TXD[1:0], TX_EN Input Time rise

0.02

0.15

ns

4, 5

TXD[1:0], TX_EN Input Time fall

0.02

0.15

ns

4, 5

Notes:

1. Clock Duty cycle measurement: High interval measured from Vih to Vil points, Low from Vil to next Vih

2. Clock interval measurement from Vih to Vih

3. Cload = 25 pF

4. Cload = 200 fF

5. The input delay test conditions: Maximum input level = VIN = 2.7V; Input rise/fall time (0.2VIN to 0.8VIN)

= 1ns (Slew Rate ~ 1.5ns).

6. The NC-SI specification defines a hold time of 1.0 ns. In order to work with the 82575, the board designer

should guarantee a hold time of 1.5 ns.

SMBus Interface

SMBus AC Characteristics (master mode)

Symbol

FSMB

TBUF

THD:STA

TSU:STA

TSU:STO

THD:DAT

TTIMEOUT

TLOW

Parameter

SMBus Frequency

Time between STOP and START

condition driven by the device

Hold time after Start Condition. After

this period, the first clock is generated.

Start Condition setup time

Stop Condition setup time

Data hold time

Detect SMBClk low timeout

SMBClk low time

Min

26.2

Typ

74.4

6.56

6.72

6.88

0.48

5.76

Max

100

31.5

Units

kHz

µs

µs

µs

µs

µs

ms

µs

53

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