78M6631-IM(2012_04) Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
78M6631-IM Datasheet PDF : 30 Pages
| |||
DS_6631_056
78M6631 Data Sheet
1.10 Oscillator
The 78M6631 oscillator drives a standard 32.768 kHz quartz crystal. These crystals are accurate and do
not require a high-current oscillator circuit. The 78M6631 oscillator has been designed specifically to
handle these crystals and is compatible with their high impedance and limited power handling capability.
The oscillator is powered directly and only from V3P3D, which therefore must be connected to a DC
voltage source not to exceed 4 V.
Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.
1.11 PLL and Internal Clock Generation
Timing for the device is derived from the 32.768 kHz crystal oscillator output. The PLL and on-chip timing
functions provide several clocks which include:
The MPU clock (CKMPU)
The emulator clock (2 x CKMPU)
The clock for the CE (CKCE)
The delta-sigma ADC and FIR clock(CKADC, CKFIR)
These internal clocks can be adjusted for various programmable rates which affect device functionality.
Refer to the 78M6631 Programmer’s Reference Manual for more information regarding the
programmability of the 78M6631 PLL and internal clock generation modules.
1.12 Real-Time Clock (RTC)
The RTC circuit is driven directly by the crystal oscillator. The RTC consists of a counter chain and output
registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month,
month, and year (including leap years). Refer to the 78M6631 Programmer’s Reference Manual for more
information regarding the use of the 78M6631 RTC.
1.13 Hardware Watchdog Timer
V3P3
V3P3 - 10mV
V3P3 -
400mV
VBIAS
In addition to the basic watchdog timer included in the 80515 MPU, an
V1
independent, robust, fixed-duration, watchdog timer (WDT) is included in
WDT dis-
abled
the device. It uses the crystal oscillator as its time base and must be
refreshed by the MPU firmware at least every 1.5 seconds. When not
refreshed on time the WDT overflows, and the part is reset as if the RESET
pin were pulled high, except that the IORAM bits are maintained. 4096
Normal oscillator cycles (or 125 ms) after the WDT overflow, the MPU is launched
operation,
WDT
from program address 0x0000. Asserting ICE_E deactivates the WDT.
enabled
The WDT can also be disabled by connecting the V1 pin to V3P3D. This
also deactivates V1 power fault detection. Since there is no method in
firmware to disable the crystal oscillator or the WDT, it is guaranteed that
whatever state the part might find itself in, upon watchdog overflow, the part
Battery
modes
is reset to a known state.
0V
Figure 3: Functions Defined by V1
Rev 2
11
Share Link: 