74LVQ174MTR_01 Ver la hoja de datos (PDF) - STMicroelectronics

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74LVQ174MTR_01

HEX D-TYPE FLIP FLOP WITH CLEAR

STMicroelectronics 

74LVQ174

HEX D-TYPE FLIP FLOP WITH CLEAR

s HIGH SPEED:

fMAX = 150 MHz (TYP.) at VCC = 3.3 V

s COMPATIBLE WITH TTL OUTPUTS

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s LOW NOISE:

VOLP = 0.3V (TYP.) at VCC = 3.3V

s 75Ω TRANSMISSION LINE DRIVING

CAPABILITY

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

s PCI BUS LEVELS GUARANTEED AT 24 mA

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 174

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVQ174 is a low voltage CMOS HEX

D-TYPE FLIP FLOP WITH CLEAR NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

SOP

TSSOP

ORDER CODES

PACKAGE

SOP

TSSOP

TUBE

74LVQ174M

T&R

74LVQ174MTR

74LVQ174TTR

technology. It is ideal for low power and low noise

3.3V applications.

Information signals applied to D inputs are

transferred to the Q outputs on the positive going

edge of the CLK pulse.

When the CLR input is held low, the Q outputs are

held low independently of the other inputs.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

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