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74LVC4245APW Ver la hoja de datos (PDF) - Philips Electronics

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74LVC4245APW Datasheet PDF : 16 Pages
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Philips Semiconductors
Octal dual supply translating transceiver; 3-state
Product specification
74LVC4245A
FEATURES
In accordance with JEDEC
standard no. 8-1A
Wide supply voltage range:
3 V port: 1.5 to 3.6 V
5 V port: 1.5 to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs accept voltages up
to 5.5 V.
DESCRIPTION
The 74LVC4245A is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74LVC4245A is an octal dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive
directions. It is designed to interface between a 3 and 5 V bus in a mixed 3/5 V
supply environment.
The 74LVC4245A features an output enable (OE) input for easy cascading and
a send/receive (DIR) input for direction control. (OE) controls the outputs so
that the buses are effectively isolated.
In suspend mode, when VCCA is zero, there will be no current flow from one
supply to the other supply. The A-outputs must be set 3-state and the voltage
on the A-bus must be smaller than Vdiode (typ. 0.7 V). VCCA VCCB (except in
suspend mode).
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
tPHL/tPLH
CI/O
CPDA
CPDB
PARAMETER
propagation delay
An to Bn
Bn to An
input/output capacitance
A port
An to Bn
Bn to An
B port
An to Bn
Bn to An
CONDITIONS
CL = 50 pF
VCCA = 5.0 V
VCCB = 3.3 V
VI = GND to VCC; note 1
VI = GND to VCC; note 1
VI = GND to VCC; note 1
VI = GND to VCC; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
TYPICAL
UNIT
4.0
ns
4.0
ns
10.0
pF
7.8
pF
27.9
pF
26
pF
10.4
pF
1999 Jun 15
2

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