74HC7404 Ver la hoja de datos (PDF) - Philips Electronics

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Fabricante

74HC7404

5-Bit x 64-word FIFO register; 3-state

Philips Electronics 

Philips Semiconductors

5-Bit x 64-word FIFO register; 3-state

Master reset applied with FIFO full

Product specification

74HC/HCT7404

handbook, halfpage

MR INPUT

2

DIR OUTPUT

1

DOR OUTPUT

VM (1)

tW

t PLH

VM (1)

3

t PHL

4

VM (1)

t PHL

Qn OUTPUT

5

MGA668

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.9 Waveforms showing the MR input to DIR, DOR and Qn output propagation delays and the MR pulse width.

Notes to Fig.9

1. DIR LOW, output ready HIGH; assume FIFO is full

2. MR pulse LOW; clears FIFO

3. DIR goes HIGH; flag indicates input prepared for valid data

4. DOR goes LOW; flag indicates FIFO empty

5. Qn outputs go LOW (only last bit will be reset).

September 1993

14

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