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29LV160TE

FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT

Fujitsu 

MBM29LV160TE/BE-70/90/12

s COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in an improper sequence will reset the device to the

read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both

Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that

commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.

• Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor

read cycles retrieve array data from the memory. The device remains enabled for reads until the command

register contents are altered.

The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Charac-

teristics and Waveforms for specific timing parameters. (See Figure 5.1.)

• Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufactures and device codes must be accessible while the device resides in the target system. PROM

programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol-

lowing the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read

cycle from address XX01H for ×16 (XX02H for ×8) retrieves the device code (MBM29LV160TE = C4H and

MBM29LV160BE = 49H for ×8 mode; MBM29LV160TE = 22C4H and MBM29LV160BE = 2249H for ×16 mode).

(See Tables 4.1 and 4.2.)

All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit.

The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8).

Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce

a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin

mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,

also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command

sequence.

• Byte/Word Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.

Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the

rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system

is not required to provide further controls or timings. The device will automatically provide adequate internally

generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the device return to the read mode and addresses are no longer latched. (See Table 8, Hardware

Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.

Hence, Data Polling must be performed at the memory location which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occures during the

programming operation, it is impossible to guarantee whether the data being written is correct or not.

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