MX29F1610MC-12C3 Ver la hoja de datos (PDF) - Macronix International
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MX29F1610MC-12C3 Datasheet PDF : 37 Pages
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MX29F1610
LOW VCC WRITE INHIBIT
WRITE PULSE "GLITCH" PROTECTION
To avoid initiation of a write cycle during VCC power-up
and power-down, a write cycle is locked out for VCC
less than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO,
the command register is disabled and all internal
program/erase circuits are disabled. Under this condition
the device will reset to the read mode. Subsequent
writes will be ignored until the VCC level is greater than
VLKO. It is the user's responsibility to ensure that the
control pins are logically correct to prevent unintentional
write when VCC is above VLKO.
Noise pulses of less than 10ns (typical) on CE or WE
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART
START
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data A0H Address 5555H
Write Program Data/Address
Loading End?
YES
Wait 100us
Read Status Register
NO
SR7 = 1
?
YES
NO
SR4 = 0
?
YES
NO
Page Program Completed
YES
Program
another page?
NO
Operation Done, Device Stays At Read S.R. Mode
Program Error
To Continue Other Operations,
Do Clear S.R. Mode First
Note : S.R. Stands for Status Register
P/N:PM0260
16
This Material Copyrighted by Its Respective Manufacturer
REV. 2.3, APR. 16, 1999
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