MX29F1610MC-12C3 Ver la hoja de datos (PDF) - Macronix International
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MX29F1610MC-12C3 Datasheet PDF : 37 Pages
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MX29F1610
SLEEP MODE
The MX29F1610 features two software controlled low-
power modes : Sleep and Abort modes. Sleep mode is
allowed during any current operations except that once
Suspend command is issued, Sleep command is
ignored. Abort mode is excuted only during Page
Program and Chip/Sector Erase mode.
To activate Sleep mode, a three-bus cycle operation is
required. The C0H command (Refer to table 3) puts the
device in the Sleep mode. Once in the Sleep mode and
with CMOS input level applied, the power of the device
is reduced to deep power-down current levels. The only
power consumed is diffusion leakage, transistor sub-
threshold conduction, input leakage, and output leakage.
The Sleep command allows the device to COMPLETE
current operations before going into Sleep mode. Once
current operation is done, device stays at read status
register mode, RY/BY returns to ready state. The status
registers are not reset during sleep command. Program
or erase fail bit may have been set if during program/
erase mode the device retry exceeds maximum count.
During Sleep mode, the status registers, Silicon ID
codes remain valid and can still be read. The Device
Sleep Status bit - DQ2 will indicate that the device in the
sleep mode.
Writing the Read Array command wakes up the device
out of sleep mode. DQ2 is reset to "0" and Device
returns to standby current level.
ABORT MODE
To activate Abort mode, a three-bus cycle operation is
required. The E0H command (Refer to table 3) only
stops Page program or Sector /Chip erase operation
currently in progress and puts the device in Sleep mode.
But unlike the sleep command, the program or erase
operation will not be completed. Since the data in some
page/sectors is no longer valid due to an incomplete
program or erase operation, the program fail (DQ4) or
erase fail (DQ5)bit will be set.
After the abort command is executed and with CMOS
input level applied, the device current is reduced to the
same level as in deep power-down or sleep modes.
Device stays at read status register mode, RY/BY
returns to ready state.
During Abort mode, the status registers, Silicon ID
codes remain valid and can still be read. The Device
Sleep Status bit - DQ2 will indicate that the device in the
sleep mode.
Similar to the sleep mode, A read array command
MUST be written to bring the device out of the abort
state without incurring any wake up latency. Note that
once device is waken up, Clear status register mode is
required before a program or erase operation can be
executed.
RY/BY PIN AND PROGRAM/ERASE
POLLING
RY/BY is a full CMOS output that provides a hardware
method of detecting page program and sector erase
completion. It transitions to VIL after a program or erase
command sequence is written to the MX29F1610, and
returns to VOH when the WSM has finished executing
the internal algorithm.
RY/BY can be connected to the interrupt input of the
system CPU or controller. It is active at all times, not
tristated if the CE or OE inputs are brought to VIH. RY/
BY is also VOH when the device is in erase suspend or
deep power-down modes.
RY/BY pin is not provided in 44-pin SOP package.
DATA PROTECTION
The MX29F1610 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read Array
mode. Also, with its control register architecture,
alteration of the memory contents only occurs after
successful completion of specific multi-bus cycle
command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
P/N:PM0260
15
This Material Copyrighted by Its Respective Manufacturer
REV. 2.3, APR. 16, 1999
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