MX29F1610MC-12C3 Ver la hoja de datos (PDF) - Macronix International
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MX29F1610MC-12C3 Datasheet PDF : 37 Pages
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MX29F1610
READ STATUS REGISTER
The MXIC's16 Mbit flash family contains a status register
which may be read to determine when a program or
erase operation is complete, and whether that operation
completed successfully. The status register may be
read at any time by writing the Read Status command
to the CIR. After writing this command, all subsequent
read operations output data from the status register
until another valid command sequence is written to the
CIR. A Read Array command must be written to the CIR
to return to the Read Array mode.
The status register bits are output on DQ2 - DQ7(table
6) whether the device is in the byte-wide (x8) or word-
wide (x16) mode for the MX29F1610. In the word-wide
mode the upper byte, DQ(8:15) is set to 00H during a
Read Status command. In the byte-wide mode, DQ(8:14)
are tri-stated and DQ15/A-1 retains the low order address
function. DQ0-DQ1 is set to 0H in either x8 or x16 mode.
It should be noted that the contents of the status register
are latched on the falling edge of OE or CE whichever
occurs last in the read cycle. This prevents possible bus
errors which might occur if the contents of the status
register change while reading the status register. CE
or OE must be toggled with each subsequent status
read, or the completion of a program or erase operation
will not be evident.
The Status Register is the interface between the
microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate the
status of the WSM, and will also hold the bits indicating
whether or not the WSM was successful in performing
the desired operation. The WSM sets status bits four
through seven and clears bits six and seven, but cannot
clear status bits four and five. If Erase fail or Program
fail status bit is detected, the Status Register is not
cleared until the Clear Status Register command is
written. The MX29F1610 automatically outputs Status
Register data when read after Chip Erase, Sector
Erase, Page Program or Read Status Command write
cycle. The default state of the Status Register after
powerup and return from deep power-down mode is
(DQ7, DQ6, DQ5, DQ4) = 1000B. DQ3 = 0 or 1 depends
on sector-protect status, can not be changed by Clear
Status Register Command or Write State Machine.
DQ2 = 0 or 1 depends on Sleep status, During Sleep
mode or Abort mode DQ2 is set to "1"; DQ2 is reset to
"0" by Read Array command.
CLEAR STATUS REGISTER
The Eraes fail status bit (DQ5) and Program fail status
bit (DQ4) are set by the write state machine, and can
only be reset by the system software. These bits can
indicate various failure conditions(see Table 6). By
allowing the system software to control the resetting of
these bits, several operations may be performed (such
as cumulatively programming several pages or erasing
multiple blocks in squence). The status register may
then be read to determine if an error occurred during
that programming or erasure series. This adds flexibility
to the way the device may be programmed or erased.
Additionally, once the program(erase) fail bit happens,
the program (erase) operation can not be performed
further. The program(erase) fail bit must be reset by
system software before further page program or sector
(chip) erase are attempted. To clear the status register,
the Clear Status Register command is written to the
CIR. Then, any other command may be issued to the
CIR. Note again that before a read cycle can be
initiated, a Read command must be written to the CIR to
specify whether the read data is to come from the Array,
Status Register or Silicon ID.
P/N:PM0260
12
This Material Copyrighted by Its Respective Manufacturer
REV. 2.3, APR. 16, 1999
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