28F256L18 Ver la hoja de datos (PDF) - Numonyx -> Micron
Número de pieza
componentes Descripción
Fabricante
28F256L18 Datasheet PDF : 106 Pages
| |||
Numonyx™ StrataFlash® Wireless Memory (L18)
Table 2:
WAIT
WP#
ADV#
R-UB#
R-LB#
RST#
P-Mode
VPP,
VPEN
F1-VCC
F2-VCC
S-VCC
P-VCC
VCCQ
VSS
RFU
DU
NC
Device Signal Descriptions for SCSP (Sheet 2 of 2)
Output
Input
Input
Input
Input
Input
Power/
Input
Power
Power
Power
Power
Power
—
—
—
FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL,
WAIT’s active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is
VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of
the selected flash die. WP#-low enables the lock-down mechanism - locked down blocks cannot be
unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked
down blocks to be unlocked with software commands.
FLASH ADDRESS VALID: Active-low input. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
RAM UPPER / LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM
high order bytes on DQ[15:8], and R-LB#-low enables the RAM low-order bytes on DQ[7:0].
Treat this signal as NC (No Connect) for this device.
FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations.
RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode.
PSRAM MODE: Low-true; P-MODE is used to program the configuration register, and enter/exit low
power mode.
Treat this signal as NC (No Connect) for this device.
Flash Program/Erase Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should
not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPLmin. VPP must remain above VPPLmin
to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at
9 V may reduce block cycling capability.
VPEN (Erase/Program/Block Lock Enables) is not available for L18 products.
Flash Logic Power: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power
to the core logic of flash die #2. Write operations are inhibited when VCC ≤ VLKO. Device operations at
invalid VCC voltages should not be attempted.
SRAM Power Supply: Supplies power for SRAM operations.
Treat this signal as NC (No Connect) for this device.
PSRAM Power Supply: Supplies power for PSRAM operations.
Treat this signal as NC (No Connect) for this device.
Flash I/O Power: Supply power for the input and output buffers.
Ground: Connect to system ground. Do not float any VSS connection.
Reserved for Future Use: Reserve for future device functionality/ enhancements. Contact Numonyx
regarding their future use.
Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
No Connect: No internal connection; can be driven or floated.
4.3
Memory Map
See Table 3 and Table 5. The memory array is divided into multiple partitions; one
parameter partition and several main partitions:
• 128-Mbit device. This contains sixteen partitions: one 8-Mbit parameter partition,
fifteen 8-Mbit main partitions.
Datasheet
20
November 2007
251902-12
Share Link: 