21555 Ver la hoja de datos (PDF) - Intel
Número de pieza
componentes Descripción
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21555 Datasheet PDF : 60 Pages
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Non-Transparent PPB
3.3
DC Specifications
Table 7 defines the DC parameters met by all 21555 signals under the conditions of the functional
operating range.
Note: In Table 7, currents into the chip (chip sinking) are denoted as positive (+) current. Currents from
the chip (chip sourcing) are denoted as negative (–) current.
Table 7. DC Parameters
Symbol Parameter
Condition
Minimum
Maximum
Vcc
Vil
Vih
Vol
Vol5V
Voh
Voh5V
Iil
Cin
CIDSEL
Cclk
Supply voltage
Low-level input voltagea
High-level input voltagea
Low-level output voltageb
Low-level output voltagec
High-level output voltageb
High-level output voltagec
Low-level input leakage currenta,d
Input pin capacitance
p_idsel pin capacitance
p_clk, s_clk pin capacitance
—
—
—
Iout = 1500 µA
Iout = 6 mA
Iout = –500 µA
Iout = –2 mA
0 <Vin <Vcc
—
—
—
3.0
–0.5
0.5 Vcc
—
—
0.9 Vcc
2.4
—
—
—
5.0
3.6
0.3 Vcc
VIO + 0.5 V
0.1 Vcc
0.55
—
—
±10
10.0
8.0
12.0
a. Guarantees meeting the specification for the 5-V signaling environment.
b. For 3.3-V signaling environment.
c. For 5-V signaling environment.
d. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
Unit
V
V
V
V
V
V
V
µA
pF
pF
pF
3.4
3.4.1
AC Timing Specifications
The next sections specify the AC characteristics met by all 21555 signals under the conditions of
the functional operating range:
• Clock timing.
• PCI signal timing.
• Reset timing.
• Serial ROM timing.
• Parallel ROM timing.
• JTAG timing.
Clock Timing Specifications
The AC specifications consist of input requirements and output responses. The input requirements
consist of setup and hold times, pulse widths, and high and low times. The output responses are
delays from clock to signal. The AC specifications are defined separately for each clock domain
within the 21555.
Datasheet
23
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