HYB511000BJL-50 Ver la hoja de datos (PDF) - Infineon Technologies

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HYB511000BJL-50

1 M×1-Bit Dynamic RAM Low Power 1 M×1-Bit Dynamic RAM

Infineon Technologies 

HYB 511000BJ/BJL-50/-60/-70

1 M × 1-DRAM

Test Mode

The HYB 511000B/BL is the RAM organized 1 048 576 words by 1-bit, it is internally organized

262 144 words by 4-bit. In “Test Mode”, data would be written into a number of sectors (4 sectors)

in parallel and retrieved the same way. If upon reading, all bits are equal (all “H” or “L”), the data

output pin indicates a same data as all bits. In this case, the data output pin indicates an expected

data for good parts, the data output pin indicates a complementary data for bad parts. And also, if

any of the bits differed, the data output pin would indicate a high impedance state for bad parts. The

next figure shows the block diagram including its truth table when “Test Mode” is used.

In test mode, 1M DRAM can be tested as if it were 256K DRAM by the following method.

“Test Mode” function is performed on any of the timing cycles including fast page mode when “TF”

pin is held on “super voltage (VCC + 4.5 V (VCC = 5 V ± 10 %), max. voltage = 10.5 V)” for the

specified period (tTES , tTEHR and tTEHC ; see next figure). The address input of A9 is ignored in the

“Test Mode”. On the other hand, normal operation requires the “TF” pin be connected to VIL(TF)

level, or left unconnected on the printed wiring board. The “Test Mode” function reduces test times

(1/4; in case of using N test pattern).

V

IH

RAS

VIL

V

IH

CAS

VIL

tTES

V

TF

IH,TF

VIL,TF

Test Mode Cycle

tTEHC

tTEHR

Semiconductor Group

54

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