ST24LC21BM1TR(1999) Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

ST24LC21BM1TR
(Rev.:1999)

1 Kbit (x8) Dual Mode Serial EEPROM for VESA PLUG & PLAY

STMicroelectronics 

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 11. Write Modes Sequence

VCLK/WC

BYTE WRITE

VCLK/WC

PAGE WRITE

ACK

ACK

ACK

DEV SEL

BYTE ADDR

DATA IN

R/W

ACK

ACK

ACK

DEV SEL

BYTE ADDR DATA IN 1

DATA IN 2

R/W

ACK

ACK

DATA IN N

AI01893

Page Write. The Page Write mode allows up to 8

bytes to be written in a single write cycle, provided

that they are all located in the same ’row’ in the

memory: that is the most significant memory ad-

dress bits are the same. The master sends from

one up to 8 bytes of data, which are each acknow-

ledged by the memory.

After each byte is transfered, the internal byte

address counter (3 least significant bits only) is

incremented. The transfer is terminated by the

master generating a STOP condition. Care must be

taken to avoid address counter ’roll-over’ which

could result in data being overwritten. Note that, for

any write mode, the generation by the master of the

STOP condition starts the internal memory pro-

gram cycle. All inputs are disabled until the comple-

tion of this cycle and the memory will not respond

to any request.

Minimizing System Delays by Polling On ACK.

During the internal write cycle, the memory discon-

nects itself from the bus in order to copy the data

from the internal latches to the memory cells. The

maximum value of the write time (tW) is given in the

AC Characteristics table, since the typical time is

shorter, the time seen by the system may be re-

duced by an ACK polling sequence issued by the

master. The sequence is as follows:

– Initial condition: a Write is in progress (see Fig-

ure 10).

– Step 1: the Master issues a START condition

followed by a Device Select byte (1st byte of

the new instruction).

14/21

Share Link: