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89LPC933

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs

NXP Semiconductors. 

NXP Semiconductors

P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

Table 4. Pin description …continued

Symbol

Pin

Type

TSSOP28, HVQFN28

PLCC28

P3.0 to P3.1

I/O

P3.0/XTAL2/ 9

5

I/O

CLKOUT

O

O

P3.1/XTAL1 8

4

I/O

I

VSS

7

3

I

VDD

21

17

I

Description

Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.

During reset Port 3 latches are configured in the input only mode with the

internal pull-up disabled. The operation of Port 3 pins as inputs and

outputs depends upon the port configuration selected. Each port pin is

configured independently. Refer to Section 8.13.1 “Port configurations”

and Table 11 “Static characteristics” for details.

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

P3.0 — Port 3 bit 0.

XTAL2 — Output from the oscillator amplifier (when a crystal oscillator

option is selected via the flash configuration.

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -

TRIM.6). It can be used if the CPU clock is the internal RC oscillator,

watchdog oscillator or external clock input, except when XTAL1/XTAL2

are used to generate clock source for the RTC/system timer.

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits

(when selected via the flash configuration). It can be a port pin if internal

RC oscillator or watchdog oscillator is used as the CPU clock source, and

if XTAL1/XTAL2 are not used to generate the clock for the RTC/system

timer.

Ground: 0 V reference.

Power supply: This is the power supply voltage for normal operation as

well as Idle and Power-down modes.

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P89LPC933_934_935_936

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 8 — 12 January 2011

© NXP B.V. 2011. All rights reserved.

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