ADE7758ARWRL Ver la hoja de datos (PDF) - Analog Devices
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ADE7758ARWRL Datasheet PDF : 72 Pages
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ADE7758
Data Sheet
Parameter1, 2
LOGIC OUTPUTS
IRQ, DOUT, and CLKOUT
Output High Voltage, VOH
Output Low Voltage, VOL
APCF and VARCF
Output High Voltage, VOH
Output Low Voltage, VOL
POWER SUPPLY
AVDD
DVDD
AIDD
DIDD
Specification
4
0.4
4
1
4.75
5.25
4.75
5.25
8
13
1 See the Typical Performance Characteristics.
2 See the Terminology section for a definition of the parameters.
3 See the Analog Inputs section.
Unit
V min
V max
V min
V max
V min
V max
V min
V max
mA max
mA max
Test Conditions/Comments
DVDD = 5 V ± 5%
IRQ is open-drain, 10 kΩ pull-up resistor
ISOURCE = 5 mA
ISINK = 1 mA
ISOURCE = 8 mA
ISINK = 5 mA
For specified performance
5 V − 5%
5 V + 5%
5 V − 5%
5 V + 5%
Typically 5 mA
Typically 9 mA
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C.
Table 2.
Parameter1, 2
WRITE TIMING
t1
t2
t3
t4
t5
t6
t7
t8
READ TIMING
t9 3
t10
t11 4
t12 5
t135
Specification
50
50
50
10
5
1200
400
100
4
50
30
100
10
100
10
Unit
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
μs (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
Test Conditions/Comments
CS falling edge to first SCLK falling edge
SCLK logic high pulse width
SCLK logic low pulse width
Valid data setup time before falling edge of SCLK
Data hold time after SCLK falling edge
Minimum time between the end of data byte transfers
Minimum time between byte transfers during a serial write
CS hold time after SCLK falling edge
Minimum time between read command (that is, a write to communication register) and
data read
Minimum time between data byte transfers during a multibyte read
Data access time after SCLK rising edge following a write to the communications register
Bus relinquish time after falling edge of SCLK
Bus relinquish time after rising edge of CS
1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
2 See the timing diagrams in Figure 3 and Figure 4 and the Serial Interface section.
3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.
4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted here is the true bus relinquish time of the part and is
independent of the bus loading.
Rev. E | Page 6 of 72
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