MX25L1606EM1I-12G Ver la hoja de datos (PDF) - Macronix International
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MX25L1606EM1I-12G Datasheet PDF : 51 Pages
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MX25L8006E
MX25L1606E
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no
longer accepted for execution and the SRWD bit and Block Protect bits (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) are read
only.
Status Register for MX25L8006E
bit7
bit6
bit5
SRWD (status
register write
0
0
protect)
bit4
BP2
(level of
protected
block)
1=status
register write
0
disable
0
(note 1)
Non-volatile
bit
0
0
Non-volatile
bit
note 1: see the table "Protected Area Size".
bit3
BP1
(level of
protected
block)
(note 1)
Non-volatile
bit
bit2
BP0
(level of
protected
block)
(note 1)
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable (write in
latch) progress bit)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
volatile bit volatile bit
Status Register for MX25L1606E
bit7
bit6
bit5
SRWD (status
register write
0
protect)
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
1=status
register write
0
disable
(note 1)
(note 1)
Non-volatile
bit
0
Non-volatile Non-volatile
bit
bit
note 1: see the table "Protected Area Size".
bit3
BP1
(level of
protected
block)
(note 1)
Non-volatile
bit
bit2
BP0
(level of
protected
block)
(note 1)
Non-volatile
bit
bit1
bit0
WEL
WIP
(write enable (write in
latch) progress bit)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
volatile bit volatile bit
(4) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits to de-
fine the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write
Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be execut-
ed once the Hardware Protected Mode (HPM) is entered.
The sequence is shown as Figure 14.
The WRSR instruction has no effect on b6, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
P/N: PM1548
REV. 1.2, JUL. 02, 2010
17
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