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RT8885A Ver la hoja de datos (PDF) - Richtek Technology

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RT8885A Datasheet PDF : 59 Pages
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Operation
The RT8885A adopts G-NAVPTM (Green-Native AVP),
which is a Richtek proprietary topology derived from finite
DC gain compensator in constant on-time control mode.
G-NAVPTM is based on the finite gain peak current mode
with CCRCOT (Constant Current Ripple Constant On-Time)
topology. The control loop consists of PWM modulators
with power stages, current sense amplifiers and an error
amplifier as shown in functional block diagram. The
HS_FET on-time is determined by CCRCOT on-time
generator. Low offset current sense amplifiers are used
for current balance, loop control and over current detection.
RT8885A
By increasing the loading current, the current signal is
rose to increase the steady state COMP voltage, and then
the output voltage is decreased to achieving AVP.
A near-DC offset canceling is added to the output of EA to
eliminate the inherent output offset of finite gain peak
current mode controller. After EN go high, the internal ADC
sense pin setting for VINITAL, ICCMAX, over current
protection and internal compensation ramp setting. The
internal ADC also sense IMON and TSEN pin voltage for
INTEL reporting.
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS8885A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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