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RT8885A

Dual Output 3-Phase + 2-Phase PWM Controller For CPU and GPU Core Power Supply

Richtek Technology 

RT8885A

Functional Pin Description

Pin No.

1

2

Pin Name

PWMA2

TONSETA

Pin Function

GFX VR Channel 2 PWM Signal Output. Connect this pin to the PWM input

of external MOSFET driver for channel 2 of GFX VR.

GFX VR PWM On-Time Setting Pin. Connect this pin to input voltage VIN via

a resistor to set the ripple size of GFX VR output in CCM.

3, 5

ISENA[2:1]P

Positive Current Sense Input for Channel 2 and Channel 1 of GFX VR.

Negative Current Sense Input Pin for Channel 2 and Channel 1 of GFX VR.

4, 6

ISENA[2:1]N

ISENA2N can be pulled high to VCC to disable GFX VR channel 2. Connect

to this pin with a sense resistor of 680.

7

COMPA

GFX VR Compensation Pin. This pin is the output of the error amplifier.

8

FBA

9

RGNDA

GFX VR Output Voltage Feedback Pin. Connect this pin to the CPU voltage

remote sense pin with a resistor. This pin is the inverting input node of the

error amplifier.

Return Ground for GFX VR. This pin is the inverting input node for differential

remote voltage sensing.

10

IMONA

GFX VR Current Monitor Output. Connect a thermally compensated resistor

network from this pin to VREF/QRTH pin. IMONA pin output voltage VIMONA

is proportional to the total output current of GFX VR.

11

VSENA

GFX VR Output Voltage Sensing Pin. Voltage on this pin is monitored for

voltage-related protections.

12

VDIO

13

ALERT

Data Transmission Line of SVID Interface. This pin has an open drain

structure. Pull high this pin to platform VCCIO rail with a resistor placed close

to controller.

Alert Line of the SVID Interface (Active Low). This pin has an open drain

structure. Pull high this pin to platform VCCIO rail with a resistor placed close

to controller.

14

VCLK

Clock Signal Line of SVID Interface. This pin has an open drain structure. Pull

high VCLK to platform VCCIO rail with a resistor placed close to controller.

15

VRA_READY

GFX VR Power Good Indicator Output. This pin has an open drain structure.

Pull high this pin to platform VCCIO rail with a resistor.

16

VR_READY

CORE VR Power Good Indicator Output. This pin has an open drain

structure. Pull high this pin to platform VCCIO rail with a resistor.

17

VRHOT

Thermal Throttling Output (Active Low). This pin has an open drain structure.

Pull high this pin to platform VCCIO rail with a resistor.

18

IBIAS

Internal Bias Current Setting Pin. Connect this pin to GND only with a 53.6k

resistor placed close to the controller.

This Pin Provides Two Functions for GFX VR : Thermal Monitor Input, and

19

TSENA/ZLLA

Droop Enable/Disable Setting. Connect a thermally compensated resistive

voltage divider from VCC to GND and connect the joint of the voltage divider

to this pin.

CORE VR and GFX VR Over Current Protection Threshold Setting Pin.

Connect a resistive voltage divider from VCC to GND and connect the joint of

20

OCSET

the voltage divider to this pin to set summed total over current protection

threshold and per phase over current protection threshold for CORE VR and

GFX VR individually.

21

AGND

Analog Ground Pin.

This Pin Provides Two Functions for CORE VR : Thermal Monitor Input, and

22

TSEN/ZLL

Droop Enable/Disable Setting. Connect a thermally compensated resistive

voltage divider from VCC to GND and connect the joint of the voltage divider

to this pin.

Copyright ©2014 Richtek Technology Corporation. All rights reserved.

DS8885A-01 January 2014

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

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