5P49V5901BDDDNLGI Ver la hoja de datos (PDF) - Integrated Device Technology
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5P49V5901BDDDNLGI Datasheet PDF : 37 Pages
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5P49V5901 DATASHEET
t6
Clock Jitter
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
differential outputs (1.8V to 3.3V nominal
output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
Cycle-to-Cycle jitter (Peak-to-Peak),
multiple output frequencies switching,
LVCMOS outputs (1.8 to 3.3V nominal
output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 5MHz
integration range) reference clock (OUT0),
25 MHz LVCMOS outputs (1.8 to 3.3V
nominal output voltage).
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 20MHz
integration range) differential output, VDDO
= 3.465V, 25MHz crystal, 156.25MHz
output frequency
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
46
ps
74
ps
0.5
ps
0.75
1.5
ps
t7
Output Skew
t8 3 Startup Time
Skew between the same frequencies, with
outputs using the same driver format and
phase delay set to 0 ns.
PLL lock time from power-up, measured
after all VDD's have raised above 90% of
their target value.
75
ps
10
ms
t9 4 Startup Time
PLL lock time from shutdown mode
3
4
ms
1. Practical lower frequency is determ ined by loop filter settings .
2. A slew rate of 2.75V/ns or greater s hould be s elected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from EPROM to PLL regis ters . It does not include EPROM program ming/write tim e.
4. Actual PLL lock time depends on the loop configuration.
5. Duty Cycle is only guaranteed at m ax s lew rate s ettings .
PROGRAMMABLE CLOCK GENERATOR
18
MARCH 3, 2017
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