GD25Q20 Ver la hoja de datos (PDF) - Unspecified

Número de pieza

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Fabricante

GD25Q20

GD25Q20BxIGx Uniform sector dual and quad serial flash

Unspecified 

SCLK

SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6

GD25SQO(IO210) B7x5IG3 x1 U7ni5fo3rm1 s7ec5to3r d1 u7al5an3d1qu7ad serial flash

Byte1

Byte2

Byte3

Byte4

7.10. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the

3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each

bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,

IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit

(QE) of Status RegUistneri(fSo9r) mmusSt beecsettotorenable for the Quad I/O Fast read command. To ensure optimum performance

the High PerformanDceuMaoldean(HdPMQ) cuomamdanSde(Ar3iHa)lmFulsat bsehexecuted once, prior to the QuadGI/ODF2as5tQRe4a0d cBom/2m0aBnd.

Quad I/O Fast Read With “Continuous Read Mode”

The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read

Mode” bits (M7-0) after the input 3-byte address (A23-A0). If2t3he “Continuous Read Mode” bits (M7-0) =AXH, then the next

Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The

command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than

AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read

Mode” Reset command can be used to reset (M7-0) before issuing normal command.

Figure 12. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Command

EBH

40404040

4040 4

51515151

5151 5

62626262

6262 6

73737373

A23-16 A15-8 A7-0 M7-0

Dummy

7373 7

Byte1 Byte2

Figure 13. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)

CS#

SCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SI(IO0)

40404040

4040 4

SO(IO1)

51515151

5151 5

WP#(IO2)

62626262

6262 6

HOLD#(IO3)

73737373

A23-16 A15-8 A7-0 M7-0

Dummy

7373 7

Byte1 Byte2

7.11. Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest

address bit (A0) must equal 0 and only 2-dummy clock. T3h8e c-om19mand sequence is shown in followed Figure14. TheRfeirvs.t1.1

byte addressed can be at any location. The address is automatically incremented to the next higher address after each

byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word

Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3h) must be

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