̶ One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touchscreen function
Safety
̶ Power-on Reset Cells
̶ Independent Watchdog
̶ Main Crystal Clock Failure Detection
̶ Register Write Protection
̶ SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)
̶ Memory Management Unit
Security
̶ TRNG: True Random Number Generator
̶ Encryption Engine
AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications
̶ Atmel Secure Boot Solution
I/O
̶ Five 32-bit Parallel Input/Output Controllers
̶ 160 I/Os
̶ Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input
̶ Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering
̶ Slew Rate Control on High Speed I/Os
̶ Impedance Control on DDR I/Os
Packages
̶ 324-ball LFBGA, 15 x 15 x 1.4 mm, pitch 0.8 mm
̶ 324-ball TFBGA, 12 x 12 x 1.2 mm, pitch 0.5 mm
SAMA5D3 Device Differences
Peripherals
SAMA5D31
CAN0, CAN1
–
EMAC
GMAC
–
HSMCI2
LCDC
TC1
–
UART0, UART1
SAMA5D33
–
–
–
–
–
SAMA5D34
–
–
–
SAMA5D35
–
SAMA5D36
SAMA5D3 Series [DATASHEET]
3
Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16