AD5726 Ver la hoja de datos (PDF) - Analog Devices
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AD5726 Datasheet PDF : 20 Pages
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Data Sheet
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5726 is via a serial bus
that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
interface (minimum) consisting of a clock signal, a data signal,
and a synchronization signal. The AD5726 requires a 16-bit
data-word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be
done under the control of LDAC.
MC68HC11 Interface
Figure 30 shows an example of a serial interface between the
AD5726 and the MC68HC11 microcontroller. The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1); clock polarity bit (CPOL = 0), and
the clock phase bit (CPHA = 1). The SPI is configured by writing
to the SPI control register (SPCR); see the 68HC11 User Manual.
SCK of the MC68HC11 drives the SCLK of the AD5726, the
MOSI output drives the serial data line (SDIN) of the AD5726.
The CS is driven from one of the port lines, in this case, PC7.
When data is being transmitted to the AD5726, the CS line
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle; thus,
to load the required 16-bit word, PC7 is not brought high until
the second 8-bit word has been transferred to the input shift
register of the DAC.
MC68HC11*
MOSI
AD5726*
SDIN
SCK
SCLK
PC7
CS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. MC68HC11 to AD5726 Interface
8xC51 Interface
The AD5726 requires a clock synchronized to the serial data.
For this reason, the 8xC51 must be operated in Mode 0. In this
mode, serial data is transferred through RxD, and a shift clock
is output on TxD.
P3.3 and P3.4 are bit-programmable pins on the serial port and
are used to drive CS and LDAC, respectively. The 8Cx51 provides
the LSB of its SBUF register as the first bit in the data stream. The
user must ensure that the data in the SBUF register is arranged
correctly because the DAC expects MSB first. When data is to
be transmitted to the DAC, P3.3 is taken low. Data on RxD is
clocked out of the microcontroller on the rising edge of TxD
and is valid on the falling edge. As a result, no glue logic is
required between this DAC and the microcontroller interface.
AD5726
The 8xC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 16-bit word, CS (P3.3) must be left low after the first
eight bits are transferred. After the second byte has been trans-
ferred, the P3.3 line is taken high. The DAC can be updated
using LDAC via P3.4 of the 8xC51.
8xC51*
RxD
TxD
P3.3
P3.4
AD5726*
SDIN
SCLK
CS
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 31. 8xC51 to AD5726 Interface
PIC16C6x/PIC16C7x Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit set to 0.
This is accomplished by writing to the synchronous serial port
control register (SSPCON). See the PIC16/17 Microcontroller
User Manual. In this example, I/O Port RA1 is used to pulse CS
and enable the serial port of the AD5726. This microcontroller
transfers only eight bits of data during each serial transfer opera-
tion; therefore, two consecutive write operations are needed.
Figure 32 shows the connection diagram.
PIC16C6x/
PIC16C7x*
SDO/RC5
SCLK/RC3
RA1
AD5726*
SDIN
SCLK
CS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 32. PIC16C6x/PIC16C7x to AD5726 Interface
Blackfin® DSP Interface
Figure 33 shows how the AD5726 can be interfaced to the
Analog Devices Blackfin DSP. The Blackfin processor has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5726. It also has programmable I/O pins that can
be used to set the state of a digital input such as the LDAC pin.
ADSP-BF531
AD5726*
SPISELx
SCK
MOSI
PF10
CS
SCLK
SDIN
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. Blackfin DSP to AD5726 Interface
Rev. C | Page 17 of 20
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