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OR2C26A3PS208I-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Description
mable input/output cells (PICs). An array of PLCs is
surrounded by PICs as shown in Figure 1. Each PLC
The ORCA Series 2 series of SRAM-based FPGAs are contains a programmable function unit (PFU). The
an enhanced version of the ATT2C/2T architecture.
PLCs and PICs also contain routing resources and
The latest ORCA series includes patented architectural conï¬guration RAM. All logic is done in the PFU. Each
enhancements that make functions faster and easier to PFU contains four 16-bit look-up tables (LUTs) and four
design while conserving the use of PLCs and routing
resources.
The Series 2 devices can be used as drop-in replace-
S ments for the ATT2Cxx/ATT2Txx series, respectively,
and they are also bit stream compatible with each
other. The usable gate counts associated with each
E series are provided in Table 1. Both series are offered
in a variety of packages, speed grades, and tempera-
ture ranges.
IC The ORCA series FPGA consists of two basic ele-
D ments: programmable logic cells (PLCs) and program-
latches/flip-flops (FFs).
The PLC architecture provides a balanced mix of logic
and routing that allows a higher utilized gate/PFU than
alternative architectures. The routing resources carry
logic signals between PFUs and I/O pads. The routing
in the PLC is symmetrical about the horizontal and ver-
tical axes. This improves routability by allowing a bus of
signals to be routed into the PLC from any direction.
Some examples of the resources required and the per-
formance that can be achieved using these devices are
represented in Table 2.
V Table 2. ORCA Series 2CA System Performance
E Function
E U 16-bit loadable up/down
counter
D IN 16-bit accumulator
8 x 8 parallel multiplier:
— Multiplier mode,
T unpipelined1
T — ROM mode, unpipelined2
— Multiplier mode, pipelined3
C 32 x 16 RAM:
N — Single port (read and write/
cycle)4
E — Single port5
O — Dual port6
L 36-bit parity check (internal)
32-bit address decode
E C (internal)
#
PFUs
4
Speed Grade
-3
-4
66.7 87.0
Unit
MHz
4 66.7 87.0 MHz
22 19.3 25.1 MHz
9 55.6 71.9 MHz
44 69.0 82.0 MHz
9 28.6 36.2 MHz
9 52.6 69.0 MHz
16 52.6 83.3 MHz
4 11.0 9.1 ns
3.25 9.5 7.5 ns
1.Implemented using 4 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
S IS 2. Implemented using two 16 x 12 ROMs and one 12-bit adder, one 8-bit input, one ï¬xed operand, one 16-bit output.
3. Implemented using 4 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (28 of 44 PFUs contain only pipelining registers).
4. Implemented using 16 x 4 synchronous single-port RAM mode allowing both read and write per clock cycle, including write/read address
multiplexer.
D 5. Implemented using 16 x 4 synchronous single-port RAM mode allowing either read or write per clock cycle, including write/read address mul-
tiplexer.
6. Implemented using 16 x 2 synchronous dual-port RAM mode.
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