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OR2C10A3S208I-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
®
Field-ProgrammaOblReSCGAateSeArrireasy2s Features
E â– High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
IC technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
D than 1.0 ns with -8 speed grade)
â– High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
V E â– Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
E U ■Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
D â– Eight 3-state buffers per PFU for on-chip bus structures
IN â– Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
T — Synchronous single port: 64 bits/PFU
T — Synchronous dual port: 32 bits/PFU
â– Improved ability to combine PFUs to create larger RAM
C structures using write-port enable and 3-state buffers
N â– Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
E — 8 x 8 multiplier requires only 16 PFUs
O — 30% increase in speed
■Flip-flop/latch options to allow programmable priority of
L synchronous set/reset vs. clock enable
â– Enhanced cascadable nibble-wide data path
E C capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
S IS Table 1. ORCA Series 2 FPGAs
â– Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacriï¬cing
performance
â– Upward bit stream compatible with the ORCA ATT2Cxx/
ATT2Txx series of devices
â– Pinout-compatible with new ORCA Series 3 FPGAs
â– TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
â– Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
â– Built-in boundary scan (IEEE*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
â– Multiple conï¬guration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
â– Full PCI bus compliance for all devices
â– Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ispLEVER Develop-
ment System support (for back-end implementation)
â– New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster conï¬guration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI sys-
tems
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
D OR2C04A/OR2T04A
Usable
Gates*
4,800—11,000
# LUTs Registers
400
400
Max User
RAM Bits
6,400
User
I/Os
160
Array Size
10 x 10
OR2C06A
6,900—15,900
576
576
9,216
192
12 x 12
OR2C08A/OR2T08A
9,400—21,600
784
724
12,544
224
14 x 14
OR2C10A/OR2T10A
12,300—28,300
1024
1024
16,384
256
16 x 16
OR2C12A
15,600—35,800
1296
1296
20,736
288
18 x 18
OR2C15A/OR2T15A/OR2T15B 19,200—44,200
1600
1600
25,600
320
20 x 20
OR2C26A/OR2T26A
27,600—63,600
2304
2304
36,864
384
24 x 24
OR2C40A/OR2T40A/OR2T40B 43,200—99,400
3600
3600
57,600
480
30 x 30
* The ï¬rst number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.
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