AD8000YCPZ-REEL Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD8000YCPZ-REEL

1.5 GHz Ultrahigh Speed Op Amp

Analog Devices 

AD8000

Placement of the capacitor returns (grounds), where the capaci-

tors enter into the ground plane, is also important. Returning

the capacitors grounds close to the amplifier load is critical for

distortion performance. Keeping the capacitors distance short,

but equal from the load, is optimal for performance.

In some cases, bypassing between the two supplies can help to

improve PSRR and to maintain distortion performance in

crowded or difficult layouts. This is as another option to

improve performance.

Minimizing the trace length and widening the trace from the

capacitors to the amplifier reduce the trace inductance. A series

inductance with the parallel capacitance can form a tank circuit,

which can introduce high frequency ringing at the output. This

additional inductance can also contribute to increased distor-

tion due to high frequency compression at the output. The use

of vias should be minimized in the direct path to the amplifier

power supply pins since vias can introduce parasitic inductance,

which can lead to instability. When required, use multiple large

diameter vias because this lowers the equivalent parasitic

inductance.

Data Sheet

GROUNDING

The use of ground and power planes is encouraged as a method

of proving low impedance returns for power supply and signal

currents. Ground and power planes can also help to reduce

stray trace inductance and to provide a low thermal path for the

amplifier. Ground and power planes should not be used under

any of the pins of the AD8000. The mounting pads and the

ground or power planes can form a parasitic capacitance at the

amplifiers input. Stray capacitance on the inverting input and

the feedback resistor form a pole, which degrades the phase

margin, leading to instability. Excessive stray capacitance on the

output also forms a pole, which degrades phase margin.

Rev. B | Page 16 of 20

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