S-1112B2JPI-L7PTFU Ver la hoja de datos (PDF) - Seiko Instruments Inc
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S-1112B2JPI-L7PTFU Datasheet PDF : 30 Pages
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HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1112/1122 Series
Rev.6.0_00
Explanation of Terms
1. Low dropout voltage regulator
The low dropout voltage regulator is a voltage regulator whose dropout voltage is low due to its built-in
low on-resistance transistor.
2. Low ESR
A capacitor whose ESR (Equivalent Series Resistance) is low. The S-1112/1122 Series enables use of
a low ESR capacitor, such as a ceramic capacitor, for the output-side capacitor CL. A capacitor whose
ESR is 10 Ω or less can be used.
3. Output voltage (VOUT)
The accuracy of the output voltage is ensured at ±1.0% under the specified conditions of fixed input
voltage*1, fixed output current, and fixed temperature.
*1. Differs depending the product.
Caution If the above conditions change, the output voltage value may vary and exceed the
accuracy range of the output voltage. Please see the electrical characteristics and
attached characteristics data for details.
4.
Line
regulation
⎜⎜⎝⎛
ΔV OUT1
ΔVIN •VOUT
⎟⎟⎠⎞
Indicates the dependency of the output voltage on the input voltage. That is, the values show how
much the output voltage changes due to a change in the input voltage with the output current remaining
unchanged.
5. Load regulation (ΔVOUT2)
Indicates the dependency of the output voltage on the output current. That is, the values show how
much the output voltage changes due to a change in the output current with the input voltage remaining
unchanged.
6. Dropout voltage (Vdrop)
Indicates the difference between the input voltage VIN1, which is the input voltage (VIN) at the point where
the output voltage has fallen to 98% of the output voltage value VOUT3 after VIN was gradually decreased
from VIN = VOUT(S) + 1.0 V, and the output voltage at that point (VOUT3 × 0.98).
Vdrop = VIN1 − (VOUT3 × 0.98)
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Seiko Instruments Inc.
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