CY7C1318V18 Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C1318V18 Datasheet PDF : 24 Pages
| |||
TAP Controller Block Diagram
PRELIMINARY
CY7C1316V18
CY7C1318V18
CY7C1320V18
Selection
Circuitry
TDI
0
Bypass Register
210
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . 2 1 0
Identification Register
106 . . . . 2 1 0
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[11, 12, 22]
Parameter
Description
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and OutputLoad Current
Test Conditions
IOH = −2.0 mA
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
GND ≤ VI ≤ VDD
Min.
VDD − 0.45
VDD − 0.2
0.65VDD
–0.3
−5
Max.
0.45
0.2
VDD + 0.3
0.35VDD
5
Unit
V
V
V
V
V
V
µA
TAP AC Switching Characteristics Over the Operating Range[23, 24]
Parameter
Description
Min.
Max.
Unit
tTCYC
TCK Clock Cycle Time
100
ns
tTF
TCK Clock Frequency
10
MHz
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
Notes:
22. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
23. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
24. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05177 Rev. *A
Page 19 of 24
Share Link: 