MAX6850 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX6850 Datasheet PDF : 34 Pages
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4-Wire Interfaced, 7-, 14-, and 16-Segment Alpha-
numeric Vacuum-Fluorescent Display Controller
CS
SCLK
DIN
tCSS
tCL
tCH
tDH
tDS
DN
DN-1
DOUT
Figure 8. 4-Wire Serial Interface Timing Diagram
tCSW
tCSH
tCP
tCSU
D1
D0
D15
CS
CLK
D15
=0
DIN
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
D15 = 0
Figure 9. 16-Bit Write Transmission to the MAX6850
Writing Device Registers
The MAX6850 contains a 16-bit shift register into which
DIN is clocked on the rising edge of SCLK, when CS is
low. When CS is high, transitions on SCLK have no
effect. When CS goes high, the 16 bits in the shift regis-
ter are parallel loaded into a 16-bit latch. The 16 bits in
the latch are then decoded and executed.
The MAX6850 is written to using the following
sequence:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take CS high (while SCLK is still high after clocking
in the last data bit).
5) Take SCLK low.
Figure 9 shows a write operation when 16 bits are
transmitted.
If fewer or greater than 16 bits are clocked into the
MAX6850 between taking CS low and taking CS high
again, the MAX6850 stores the last 16 bits received,
including the previous transmission(s). The general
case is when n bits (where n > 16) are transmitted to
the MAX6850. The last bits comprising bits {n-15} to {n}
are retained and are parallel loaded into the 16-bit latch
as bits D15 to D0, respectively (Figure 10).
Reading Device Registers
Any register data within the MAX6850 may be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
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