MAX5940A(2003) Ver la hoja de datos (PDF) - Maxim Integrated
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MAX5940A Datasheet PDF : 15 Pages
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IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Table 1. PD Power Classification/RCL Selection
CLASS
USAGE
0
Default
1
Optional
2
Optional
3
Optional
4
Not Allowed
*Class 4 reserved for future use.
RCL (Ω)
10k
732
392
255
178
MAXIMUM POWER USED BY PD (W)
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
Reserved*
Table 2. Setting Classification Current
CLASS
RCL (Ω)
VIN* (V)
CLASS CURRENT SEEN AT VIN (mA)
MIN
MAX
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
MIIN
MAX
0
10k
12.6 to 20
0
2
0
4
1
732
12.6 to 20
9.17
11.83
9
12
2
392
12.6 to 20
17.29
19.71
17
20
3
255
12.6 to 20
26.45
29.55
26
30
4
178
12.6 to 20
36.6
41.4
36
44
*VIN is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop.
The PSE determines the class of a PD by applying a volt-
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5940A/MAX5940B exhibit a cur-
rent characteristic with values indicated in Table 2. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification cur-
rent includes the current drawn by the 25.5kΩ detection
signature resistor and the supply current of the
MAX5940A/MAX5940B so the total current drawn by the
PD is within the IEEE 802.3af standard figures. The classi-
fication current is turned off whenever the device is in
power mode.
Power Mode
During power mode, when VIN rises above the undervolt-
age lockout threshold (VUVLO,ON), the MAX5940A/
MAX5940B gradually turn on the internal N-channel MOS-
FET Q1 (see Figure 2). The MAX5940A/MAX5940B
charge the gate of Q1 with a constant current source
(10µA, typ). The drain-to-gate capacitance of Q1 limits
the voltage rise rate at the drain of the MOSFET, thereby
limiting the inrush current. To reduce the inrush current,
add external drain-to-gate capacitance (see the Inrush
Current section). When the drain of Q1 is within 1.2V of
its source voltage and its gate-to-source voltage is
above 5V, the MAX5940A/MAX5940B asserts the
PGOOD/PGOOD outputs. The MAX5940A/MAX5940B
have a wide UVLO hysteresis and turn-off deglitch time
to compensate for the high impedance of the twisted-
pair cable.
Undervoltage Lockout
The MAX5940A/MAX5940B operate up to a 67V supply
voltage with a default UVLO turn-on (VUVLO,ON) set at
35V (MAX5940A) or 39V (MAX5940B) and a UVLO turn-
off (VUVLO,OFF) set at 30V. The MAX5940B has an
adjustable UVLO threshold using a resistor-divider con-
nected to UVLO (see Figure 3). When the input voltage
is above the UVLO threshold, the IC is in power mode
and the MOSFET is on. When the input voltage goes
below the UVLO threshold for more than tOFF_DLY, the
MOSFET turns off.
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