MAX3421EEHJ Ver la hoja de datos (PDF) -

USB Peripheral/Host Controller

with SPI Interface

occur on the positive edge of SCLK. The MAX3421E

counts bits and divides them into bytes. If fewer than 8

bits are clocked into the MAX3421E when SS goes

high, the MAX3421E discards the partial byte.

The MAX3421E SPI interface operates without adjust-

ment in either SPI mode (CPOL = 0, CPHA = 0) or

(CPOL = 1, CPHA = 1). No mode bit is required to

select between the two modes since the interface uses

the rising edge of the clock in both modes. The two

clocking modes are illustrated in Figure 16. Note that

the inactive SCLK value is different for the two modes.

Figure 16 illustrates the full-duplex mode, where data is

simultaneously clocked into and out of the MAX3421E.

SPI Half- and Full-Duplex Operation

The MAX3421E can be programmed to operate in half-

duplex (a bidirectional data pin) or full-duplex (one

data-in and one data-out pin) mode. The SPI master

sets a register bit called FDUPSPI (full-duplex SPI) to 1

for full-duplex, and 0 for half-duplex operation. Half-

duplex is the power-on default.

Full-Duplex Operation

When the SPI master sets FDUPSPI = 1, the SPI inter-

face uses separate data pins, MOSI and MISO to trans-

fer data. Because of the separate data pins, bits can

be simultaneously clocked into and out of the

MAX3421E. The MAX3421E makes use of this feature

by clocking out 8 USB status bits as the command byte

is clocked in. Figure 17 shows the status bits clocked

out in peripheral mode and Figure 18 shows the status

bits clocked out host mode.

Reading from the SPI Slave Interface (MISO)

The SPI master reads data from the MAX3421E slave

interface using the following steps:

1) When SS is high, the MAX3421E is unselected and

tri-states the MISO output.

2) After driving SCLK to its inactive state, the SPI master

selects the MAX3421E by driving SS low. The

MAX3421E turns on its MISO output buffer and places

the first data bit (Q7) on the MISO output (Figure 16).

3) The SPI master simultaneously clocks the com-

mand byte into the MAX3421E MOSI pin, and USB

status bits out of the MAX3421E MISO pin on the

rising edges of the SCLK it supplies. The

MAX3421E changes its MISO output data on the

falling edges of SCLK.

4) After eight clock cycles, the master can drive SS

high to deselect the MAX3421E, causing it to tri-

state its MISO output. The falling edge of the clock

puts the MSB of the next data byte in the sequence

on the MISO output (Figure 16).

5) By keeping SS low, the master clocks register data

bytes out of the MAX3421E by continuing to supply

SCLK pulses (burst mode). The master terminates

the transfer by driving SS high. The master must

ensure that SCLK is in its inactive state at the

beginning of the next access (when it drives SS

low). In full-duplex mode, the MAX3421E ignores

data on MOSI while clocking data out on MISO.

Writing to the SPI Slave Interface (MOSI)

The SPI master writes data to the MAX3421E slave

interface through the following steps:

1) The SPI master sets the clock to its inactive state.

While SS is high, the master can drive the MOSI input.

2) The SPI master selects the MAX3421E by driving

SS low and placing the first data bit to write on the

MOSI input.

3) The SPI master simultaneously clocks the com-

mand byte into the MAX3421E and USB status bits

out of the MAX3421E MISO pin on the rising edges

of the SCLK it supplies. The SPI master changes its

MOSI input data on the falling edges of SCLK.

4) After eight clock cycles, the master can drive SS

high to deselect the MAX3421E.

5) By keeping SS low, the master clocks data bytes

into the MAX3421E by continuing to supply SCLK

pulses (burst mode). The master terminates the

transfer by driving SS high. The master must ensure

that SCLK is inactive at the beginning of the next

access (when it drives SS low). In full-duplex mode,

the MAX3421E outputs USB status bits on MISO

during the first 8 bits (the command byte), and sub-

sequently outputs zeros on MISO as the SPI master

clocks bytes into MOSI.

Half-Duplex Operation

The MAX3421E is put into half-duplex mode at power-

on, or when the SPI master clears the FDUPSPI bit. In

half-duplex mode, the MAX3421E tri-states its MISO pin

and makes the MOSI pin bidirectional, saving a pin in

the SPI interface. The MISO pin can be left unconnect-

ed in half-duplex operation.

Because of the single data pin, the USB status bits

available in full-duplex mode are not available as the

SPI master clocks in the command byte. In half-duplex

mode these status bits are accessed in the normal way,

as register bits.

The SPI master must operate the MOSI pin as bidirec-

tional. It accesses a MAX3421E register as follows:

20 ______________________________________________________________________________________

Share Link: