MAX3421EEHJ Ver la hoja de datos (PDF) -

USB Peripheral/Host Controller

with SPI Interface

tRISE

VOH

VOL

Figure 8. Rise and Fall Times

tL

SS

tCSS

tFALL

90%

10%

Test Circuits and Timing Diagrams

MAX3421E

33Ω

D+ OR D-

TEST

POINT

CL

15kΩ

Figure 9. Load for D+/D- AC Measurements

tCL

tCH

tCSW

tT

SCLK

MOSI

MISO

HIGH

IMPEDANCE

1

2

tDS

tDH

8

9

10

tCP

tDO

16

HIGH

IMPEDANCE

Figure 10. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))

tL

SS

tCSW

tCL

tCH

tT

SCLK

MOSI

1

2

tDS

8

9

10

tCP

16

HI-Z

tDH

HIGH

MISO IMPEDANCE

tON

tDI

tOFF

HIGH

IMPEDANCE

NOTES:

1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS

FOR FULL-DUPLEX MODE.

2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.

3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-FALLING EDGE, THE MAX3421E STARTS DRIVING THE MOSI PIN AFTER TIME tON. THE EXTERNAL MASTER MUST TURN

OFF ITS DRIVER TO THE MOSI PIN BEFORE tON TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.

Figure 11. SPI Bus Timing Diagram (Half-Duplex Mode, SPI Mode (0,0))

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