M95512-DRMB3 Ver la hoja de datos (PDF) - STMicroelectronics

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M95512-DRMB3

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

M95512-W, M95512-R

Instructions

6.1

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then

enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven

high.

Figure 8. Write Enable (WREN) sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

6.2

Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction

to the device.

As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

(S) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

● Power-up

● WRDI instruction execution

● WRSR instruction completion

● WRITE instruction completion.

Figure 9. Write Disable (WRDI) sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

Doc ID 11124 Rev 13

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