M69AR048B Ver la hoja de datos (PDF) - STMicroelectronics
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M69AR048B Datasheet PDF : 29 Pages
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M69AR048B
Table 11. Read Mode AC Characteristics
M69AR048B
Symbol
Alt.
Parameter
80
85
Unit
Min Max Min Max
tAVAX (1,2,9)
tRC Address Valid Time
80 1000 85 1000 ns
tAVAX2(1,5,6,9) tPRC Page Read Cycle Time
25 1000 30 1000 ns
tAVEH2(1,5,6,9) tPRC Page Read Cycle Time
25 1000 30 1000 ns
tAVEL
tASC Address Valid to Chip Enable Low
–5
–5
ns
tAVQV (4,9)
1.65V ≤VCC ≤1.75V
tAA Address Valid to Output Valid
1.75V ≤VCC ≤1.95V
80
70
85 ns
70 ns
tAVQV2 (5,9)
tPAA Page Address Access Time
20
25 ns
tAXAV (4,7)
tAX Address Invalid Time
10
10 ns
tAXAV2 (5,7)
tAXP Page Address Invalid Time
10
10 ns
tAXQX
tOH Data hold from address change
5
5
ns
tBHQX
tOH Upper/Lower Byte Enable High to Output Transition
5
5
ns
tBHQZ
tBHZ Upper/Lower Byte Enable High to Output Hi-Z
20
20 ns
tBLQV(9)
tBA Upper/Lower Byte Enable Low to Output Valid
30
35 ns
tBLQX (3)
tBLZ Upper/Lower Byte Enable Low to Output Transition
0
0
ns
tEHAX (8)
tCHAH Chip Enable High to Address Invalid
–5
–5
ns
tEHEL
tCP Chip Enable High to Chip Enable Low
15
15
ns
tEHQX
tOH Chip Enable High to Output Transition
5
5
ns
tEHQZ
tCHZ Chip Enable High to Output Hi-Z
20
20 ns
tELAX (1,2)
tRC Read Cycle Time
80 1000 85 1000 ns
tELEH (1,2)
tRC Read Cycle Time
80 1000 85 1000 ns
tELQV(9)
tCE
Chip Enable Low to Output
Valid
1.65V ≤VCC ≤1.75V
1.75V ≤VCC ≤1.95V
80
70
85
ns
70
tELQX (3)
tCLZ Chip Enable Low to Output Transition
5
5
ns
tGHQX
tOH Output Data Hold Time
5
5
ns
tGHQZ
tOHZ Output Enable High to Output Hi-Z
20
20 ns
tGLQV(9)
tOE Output Enable Low to Output Valid
45
50 ns
tGLQX (3)
tOLZ Output Enable Low to Output Transition
0
0
ns
Note: 1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20. If needed by system operation, please
contact your local ST representative for relaxation of the 1000ns limitation.
2. Address should not be changed within minimum Read Cycle Time.
3. The output load 5pF without any other load.
4. Applicable to A3 to A20 when E1 is kept Low.
5. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access.
6. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs.
7. Applicable when at least two of address inputs among applicable are switched from previous state.
8. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied.
9. Values obtained with AC Measurement Load Circuit 1 (see Figure 5). If the test conditions correspond to AC Measurement Load
Circuit 2 (see Figure 6), 10ns must be added to the times given in the above table.
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