IA6805E2-PDW40I-00 Ver la hoja de datos (PDF) - InnovASIC, Inc
Número de pieza
componentes Descripción
Fabricante
IA6805E2-PDW40I-00 Datasheet PDF : 33 Pages
| |||
IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
Opcode Map Summary:
The following table is an opcode map for the instructions used on the MPU. The legend
following the table shows how to use the table.
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
BTB
BSC
REL
DIR
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
Hi
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Hi
Low
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111 Low
5
0
0000 BRSET0
3
BTB 2
5
BSET0
BSC 2
3
5
3
3
6
5
9
BRA
NEG NEGA NEGX NEG NEG
RTI
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX 1 INH
2
3
4
5
4
3
SUB
SUB
SUB
SUB
SUB
SUB 0 0000
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
1
0001 BRCLR0
3
BTB 2
5
BCLR0
BSC 2
3
BRN
REL
6
RTS
1 INH
2
3
4
5
4
3
CMP
CMP
CMP
CMP
CMP
CMP 1 0001
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
2
0010 BRSET1
3
BTB 2
5
BSET1
BSC 2
3
BHI
REL
2
SBC
3
SBC
4
SBC
5
SBC
4
SBC
3
SBC 2 0010
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
3
0011 BRCLR1
3
BTB 2
5
4
0100 BRSET2
3
BTB 2
5
BCLR1
BSC 2
5
BSET2
BSC 2
3
5
3
3
6
5
10
BLS
COM COMA COMX COM COM
SWI
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX 1 INH
3
5
3
3
6
5
BCC
LSR
LSRA LSRX
LSR
LSR
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
2
3
4
5
4
3
CPX
CPX
CPX
CPX
CPX
CPX 3 0011
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
2
3
4
5
4
3
AND AND AND AND AND AND 4 0100
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
5
0101 BRCLR2
3
BTB 2
5
BCLR2
BSC 2
3
BCS
REL
2
BIT
3
BIT
4
BIT
5
BIT
4
BIT
3
BIT 5 0101
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
6
5
0110 BRSET3
3
BTB 2
5
3
5
3
3
6
5
BSET3
BNE
ROR RORA RORX ROR
ROR
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
2
3
4
5
4
3
LDA
LDA
LDA
LDA
LDA
LDA 6 0110
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
7
5
0111 BRCLR3
3
BTB 2
8
5
1000 BRSET4
3
BTB 2
5
9
1001 BRCLR4
3
BTB 2
A
5
1010 BRSET5
3
BTB 2
5
B
1011 BRCLR5
3
BTB 2
C
5
1100 BRSET6
3
BTB 2
D
5
1101 BRCLR6
3
BTB 2
5
E
1110 BRSET7
3
BTB 2
5
3
5
3
3
6
5
BCLR3
BEQ
ASR
ASRA ASRX
ASR
ASR
2
TAX
4
5
6
5
4
STA
STA
STA
STA
STA 7 0111
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
1 INH
2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
3
5
3
3
6
5
BSET4
BHCC
LSL
LSLA LSLX
LSL
LSL
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
2
2
3
4
5
4
3
CLC
EOR
EOR
EOR
EOR
EOR
EOR 8 1000
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
3
5
3
3
6
5
BCLR4
BHCS
ROL ROLA ROLX ROL
ROL
2
2
3
4
5
4
3
SEC
ADC
ADC
ADC
ADC
ADC
ADC 9 1001
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BSET5
3
5
3
3
6
5
BPL
DEC DECA DECX DEC
DEC
2
2
3
4
5
4
3
CLI
ORA
ORA
ORA
ORA
ORA
ORA A 1010
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BCLR5
3
BMI
2
2
3
4
5
4
3
SEI
ADD
ADD
ADD
ADD
ADD
ADD B 1011
BSC 2 REL
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
3
5
3
3
6
5
BSET6
BMC
INC
INCA INCX
INC
INC
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
2
RSP
1 INH
2
3
4
3
2
JMP
JMP
JMP
JMP
JMP C 1100
2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BCLR6
3
4
3
3
6
4
BMS
TST
TSTA TSTX
TST
TST
2
NOP
6
BSR
5
JSR
6
JSR
7
JSR
6
JSR
5
JSR D 1101
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX
1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
5
BSET7
3
BIL
2
STOP
2
3
4
5
4
3
LDX
LDX
LDX
LDX
LDX
LDX E 1110
BSC 2 REL
1 INH
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1
IX
F
5
1111 BRCLR7
5
BCLR7
3
5
3
3
6
5
2
2
BIH
CLR CLRA CLRX CLR
CLR WAIT TXA
3
BTB 2
BSC 2
REL 2 DIR 1 INH 1 INH 2 IX1 1
IX 1 INH 1 INH
Abbreviations for Address
REL Relative
Modes:
BSC Bit set/clear
BTB Bit test and branch
INH
A
X
IMM
Inherent
Accumulator
Index Register
Immediate
IX
Indexed, no offset
IX1 Indexed, 1 byte offset
IX2 Indexed, 2 byte offset
Legend:
DIR Direct
EXT Extended
4
5
6
5
4
STX
STX
STX
STX
STX F 1111
2 DIR 3 EXT 3 IX2 2 IX1 1
IX
Mnemonic
Bytes
# of Cycles
F
1111
3
SUB
1
IX
0
0000
Opcode in Hexadecimal
Opcode in Binary
Address Mode
Copyright © 2007
©
IA211081401-03
www.Innovasic.com
Customer Support:
Page 23 of 33
1-888-824-4184
Share Link: 