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Fabricante

80C186EA13

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

Intel 

80C186EA 80C188EA 80L186EA 80L188EA

DC SPECIFICATIONS (80L186EA 80L188EA)

Symbol

Parameter

Min

Max Units

Conditions

VCC

VIL

VIH

VOL

VOH

VHYR

IIL1

Supply Voltage

27

55

V

Input Low Voltage for All Pins

Input High Voltage for All Pins

Output Low Voltage

Output High Voltage

Input Hysterisis on RESIN

b0 5

0 3 VCC

V

0 7 VCC VCC a 0 5 V

0 45

V IOL e 1 6 mA (min)

VCC b 0 5

V IOH e b1 mA (min)

0 30

V

Input Leakage Current (except

RD QSMD UCS LCS MCS0 PEREQ

MCS1 LOCK and TEST)

g10

mA 0V s VIN s VCC

IIL2

Input Leakage Current

(RD QSMD UCS LCS MCS0

MCS1 LOCK and TEST)

b275

mA VIN e 0 7 VCC

(Note 1)

IOL

Output Leakage Current

g10

mA

0 45 s VOUT s VCC

(Note 2)

ICC5

Supply Current (RESET 5 5V)

80L186EA-13

80L186EA-8

65

mA (Note 3)

40

mA (Note 3)

ICC3

Supply Current (RESET 2 7V)

80L186EA-13

80L186EA-8

34

mA (Note 3)

20

mA (Note 3)

IID5

Supply Current Idle (5 5V)

80L186EA-13

80L186EA-8

46

mA

28

mA

IID5

Supply Current Idle (2 7V)

80L186EA-13

80L186EA-8

24

mA

14

mA

IPD5

Supply Current Powerdown (5 5V)

80L186EA-13

80L186EA-8

100

mA

100

mA

IPD3

Supply Current Powerdown (2 7V)

80L186EA-13

80L186EA-8

50

mA

50

mA

COUT

CIN

Output Pin Capacitance

Input Pin Capacitance

0

15

pF TF e 1 MHz (Note 4)

0

15

pF TF e 1 MHz

NOTES

1 RD QSMD UCS LCS MCS0 MCS1 LOCK and TEST have internal pullups that are only activated during RESET

Loading these pins above IOL e b275 mA will cause the processor to enter alternate modes of operation

2 Output pins are floated using HOLD or ONCE Mode

3 Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test Conditions and with the

device in RESET (RESIN held low)

4 Output capacitance is the capacitive load of a floating output pin

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