STLC4420A Ver la hoja de datos (PDF) - STMicroelectronics
Número de pieza
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STLC4420A Datasheet PDF : 40 Pages
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Pin descriptions
STLC4420A
2.1
Signal description
Table 1. STLC4420A signal descriptions
Pin name Pin number
Type
Internal
resistor
Function
RF front end interface pins
LB_LNA_IN- D1
LB_LNA_IN+ C1
HB_LNA_IN- F1
HB_LNA_IN+ E1
LNA_SHIELD
C2, C3,D2,
E2, F2
LB_TX_OUT H1
HB_TX_OUT J1
SW1
A13
SW2
A14
SW3
A15
SW4
A16
PA_BIAS24 N2, M2
PA_BIAS5
L3
PA_RREF
PA_DET0
PA_DET1
N1, M1
B12
A12
RF input
RF input
RF input
RF input
RF shield
RF output
RF output
digital output
digital output
digital output
digital output
analog output
analog output
analog reference
analog input
analog input
100Ω RF Low band (2.4 GHz) 100Ω RF differential RX
Differential inputs.
100Ω RF High band (5 GHz) 100Ω RF differential RX
Differential inputs.
-
-
-
-
-
-
-
-
-
-
Resistor
ladder
Low noise amplifier (LNA) input shield pins.
50Ω RF transmit (TX) low band (2.4 GHz)
single ended output.
50Ω RF transmit (TX) low band (5 GHz)
single ended output.
Complementary transmit/receive
antennaswitch control outputs. I/O level
determined by VDDA supply input.
Power amplifier bias control (2.4 GHz). DAC
full-scale output current determined by
PA_RREF resistor.
Power amplifier bias control (5 GHz). DAC
full-scale output current determined by
PA_RREF resistor.
Analog reference resistor. A 20K ohm typical
resistor sets the PA_BIAS full-scale output
current.
PA Detector Input 0. (2.4 GHz)
PA Detector Input 1. (5 GHz)
Host interface and clock pins
DAT2
F24
HOST_IRQ A18
POWER_UP H23
OSC_EN
N13
1.8 V (VIO) digital
I/O
1.8 V digital
output,
VIO domain
1.8 V digital input
1.8 V digital
output
SDIO data I/O bit 2. Not used in SPI mode.
1MΩ
Pull-Down
No Pull
Host interrupt request. Typically asserted to
request a SPI data transfer. In SDIO mode
pin = DAT1.
Power up enable from host
Oscillator enable output. Initially driven high
upon powerup, under firmware control after
initialization.
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