AD7664 Ver la hoja de datos (PDF) - Analog Devices

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AD7664

16-Bit, 570 kSPS PulSAR® Unipolar CMOS ADC

Analog Devices 

AD7664

CS = 0

CNVST,

t1

RD

BUSY

t4

t3

DATABUS

PREVIOUS

CONVERSION

t 12

t 13

Figure 15. Slave Parallel Data Timing for Reading

(Read during Convert)

SERIAL INTERFACE

The AD7664 is configured to use the serial interface when the

SER/PAR is held HIGH. The AD7664 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on the SCLK pin. The output data

is valid on both the rising and falling edge of the data clock.

MASTER SERIAL INTERFACE

Internal Clock

The AD7664 is configured to generate and provide the serial data

clock SCLK when the EXT/INT pin is held LOW. The AD7664

also generates a SYNC signal to indicate to the host when the

serial data is valid. The serial clock SCLK and the SYNC signal

can be inverted, if desired. Depending on RDC/SDIN input,

the data can be read after each conversion or during the fol-

lowing conversion. Figures 16 and 17 show the detailed timing

diagrams of these two modes.

CS, RD

CNVST

EXT/INT = 0

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

t3

BUSY

SYNC

SCLK

SDOUT

t28

t30

t29

t25

t14

t18

t19

t20

t21

1

2

3

t15

X

D15

D14

t16

t22

t23

t24

t26

14

15

16

t27

D2

D1

D0

Figure 16. Master Serial Data Timing for Reading (Read after Convert)

CS, RD

CNVST

BUSY

EXT/INT = 0

t1

t3

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

SYNC

SCLK

SDOUT

t17

t14

t19

t20 t21

t15

1

2

3

t18

X

D15

D14

t25

t24

t26

14

15

16

t27

D2

D1

D0

t16

t22

t23

Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

–16–

REV. E

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