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SCAN182245A

Non-Inverting Transceiver with 25Ω Series Resistor Outputs

Fairchild Semiconductor 

SCAN ABT Live Insertion and Power Cycling Characteristics

SCAN ABT is intended to serve in Live Insertion backplane

applications. It provides 2nd Level Isolation1 which indi-

cates that while external circuitry to control the output

enable pin is unnecessary, there may be a need to imple-

ment differential length backplane connector pins for VCC

and GND. As well, pre-bias circuitry for backplane pins

may be necessary to avoid capacitive loading effects dur-

ing live insertion.

SCAN ABT provides control of output enable pins during

power cycling via the circuit in Figure 1. It essentially con-

trols the Gn pin until VCC reaches a known level.

During power-up, when VCC ramps through the 0.0V to

0.7V range, all internal device circuitry is inactive, leaving

output and I/O pins of the device in high impedance. From

approximately 0.8V to 1.8V VCC, the Power-On-Reset cir-

cuitry, (POR), in Figure 1 becomes active and maintains

device high impedance mode. The POR does this by pro-

viding a low from its output that resets the flip-flop The out-

put, Q, of the flip-flop then goes high and disables the NOR

gate from an incidental low input on the Gn pin. After 1.8V

VCC, the POR circuitry becomes inactive and ceases to

control the flip-flop. To bring the device out of high imped-

ance, the Gn input must receive an inactive-to-active transi-

tion, a high-to-low transition on Gn in this case to change

the state of the flip-flop. With a low on the Q output of the

flip-flop, the NOR gate is free to allow propagation of a Gn

signal.

During power-down, the Power-On-Reset circuitry will

become active and reset the flip-flop at approximately 1.8V

VCC. Again, the Q output of the flip-flop returns to a high

and disables the NOR gate from inputs from the Gn pin.

The device will then remain in high impedance for the

remaining ramp down from 1.8V to 0.0V VCC.

Some suggestions to help the designer with live insertion

issues:

• The Gn pin can float during power-up until the Power-

On-Reset circuitry becomes inactive.

• The Gn pin can float on power-down only after the

Power-On-Reset has become active.

The description of the functionality of the Power-On-Reset

circuitry can best be described in the diagram of Figure 2.

FIGURE 1.

1Section 7, “Design Consideration for Fault Tolerant Backplanes”, Application Note AN-881.

SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.

FIGURE 2.

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