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AN87C196KC

16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Intel 

AUTOMOTIVE 87C196KC

87C196KC B-3 STEP ERRATA

1 NMI during PTS skips an address When an NMI

interrupts a PTS routine the first byte of the in-

struction following completion of the PTS cycle is

lost This results in incorrect code execution

Workaround NMI must be disabled using exter-

nal hardware during any PTS activity

2 QBD port glitch There is a strong negative glitch

on all QBD Port pins (P1 x and P2 6 P2 7) syn-

chronous with the first falling edge of CLKOUT

This glitch lasts about 10 ns and only occurs one

time following the initial application of VCC The

time for the pin to return to VCC may be several

microseconds depending on pin loading capaci-

tance Workaround External systems and devic-

es should be disabled from responding to this

glitch until after the first CLKOUT falling edge has

occurred

3 Divide error during HOLD or READY The result

of a signed divide instruction may be off by one if

executed while the device is held off the bus by

HOLD or READY and the queue is empty Specif-

ic timings of HOLD or READY going active or in-

active must be met Workaround for HOLD dis-

able HOLD during signed divide operations (using

hardware or software) Workaround for READY

problem will only occur if unlimited wait state

mode is selected and 14 or more wait states are

inserted

4 The HSI unit has two errata one dealing with res-

olution and the other with first entries into the

FIFO

The HSI resolution is 9 states instead of 8 states

Events on the same line may be lost if they occur

faster than once every 9 state times

There is a mismatch between the 9 state time

HSI resolution and the 8 state time timer This

causes one time value to be unused every 9 timer

counts

Events may receive a time-tag on one count later

than expected because of this ‘‘skipped’’ time

value

If the first two events into an empty FIFO (not

including the Holding Register) occur in the same

internal phase both are recorded with one time-

tag Otherwise if the second event occurs within

9 states after the first its time-tag is one count

later than the first time tag If this is the ‘‘skipped’’

time value the second event’s time-tag is 2

counts later than the first’s

If the FIFO and Holding Register are empty the

first event will transfer into the Holding Register

after 8 state times leaving the FIFO empty again

If the second event occurs after this time it will

act as a new first event into an empty FIFO

DATASHEET REVISION HISTORY

The following are the key differences between this

datasheet and the -003 version

1 The ‘‘advanced information’’ status was dropped

and replaced with production status (no label)

2 Trademarks were updated

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