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PJ3842B

High Performance Current Mode Controller

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PJ3842B

High Performance Current Mode Controller

OPERATING DESCRIPTION

The PJ3842B series are high performance, fixed frequency, current mode controllers, They are speci fically designed for Off-Line

and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components . A

representative block diagram is shown in Figure 17.

OSCILLATOR

The oscillator frequen cy is programmed by the values selected fo r the timing components RT and CT. Capacitor CT is charged

from the 5.0V reference through resistor RT to approximately 2.8V and discharge to 1.2V by an internal current sink.During the

discharge o f CT , the oscillator generat es an intern al blanking pulse that holds the center input o f the NOR gate high. This causes

the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator

Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT . Note that many values of RT and C T

will give the same oscillator frequency but only onne combination will yield a specific output deadtime at a given frequency. The

oscillator thresholds are temperature compens ated, and the discharg e current is trimmed and guaranteed to within ±10% at TJ

=25℃. These internal circuit refinem ents minimum variations of oscillator frequency and maximum output duty cycle. The

results are shown in Figure 3 and 4.

In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be

accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking. The free-running oscillator

frequency should be set about 10% less than the clock frequency . A method for multi unit synchronization is shown in Figure 21.

By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.

ERROR AMPLIFIER

A fully compensated Error Ampli fier with access to the inverting input and output is provided. It features a typical DC voltage

gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees of phas e margin (Figure 7). The non-inverting input is

internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the

inverting input. The maximum input bias current is -2.0μA which can cause an output voltage error that is equal to the product of

the input bias current and the equivalent input divider source resistance.

The Error Amp Output (Pin 1) is provided for ext ernal loop compens ation (Figure 31). The output voltage is offs et by two diode

drops (≈1.4V) and divided by three before it connects to the inverting input of the Current Sense Comparator. T his guarantees that

no drive pulses appear at the Output(Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is

operating and the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum

feedb ack resistan ce is limited by the amplifier's source current (0.5mA) and the required output voltage (VOH) to reach the

comparato r’s 1.0V clamp level:

Rf(MIN) = [3.0 (1.0V)+1.4V] / 0.5mA = 8800Ω

CURRENT SENSE COMPARATOR AND PWM LATCH

The PJ3842B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated

when the peak inductor current reaches the threshold level established by the Error Ampli fier Output/Compensation (Pin 1). Thus

the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch

configuration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is

converted to a voltageby inserting the ground referen ced sense resistor RS in series with the source of output switch Q1. This

voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak

inductor current under normal operating conditions is controlled by the voltage at pin 1 where:

IPK = [V(Pin 1) - 1.4V] / 3RS

Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost, Under these

conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak swi tch

current is:

IPK (MAX) = 1.0V / RS

When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the

power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external

diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to

noise pickup can result if there is an excessive redu ction of the IPK (max) clamp voltage.

A narrow spike on the leading edge of the current waveform can usually be obs erved and may cause the power supply to exhibit

an instability when the output is lightly loaded. This spike is due to the power trans former interwinding capacitance and output

recti fier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike

duration will usually eliminate the instability: refer to Figure 26.

14-15

2002/01.ver.A

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