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PEB20320

Multichannel Network Interface Controller for HDLC

Infineon Technologies 

PEB 20320

Electrical Characteristics

The trailing edge of the reset starts the last part of the internal reset sequence and takes

about 12 SCLK cycles. It is not allowed to give an action request (AR) during these first

12 SCLK cycles after the trailing edge of signal RESET.

JTAG-Boundary Scan Timing

JTEST0 (TCK)

JTEST1 (TMS)

JTEST2 (TDI)

JTEST3 (TDO)

58

59

60

61

62

63

64

65

ITD03512

Figure 126

JTAG-Boundary Scan Timing

Table 20

Intel Bus Timing

No. Parameter

58 JTEST0 (TCK) period

59 JTEST0 (TCK) high time

60 JTEST0 (TCK) low time

61 JTEST1 (TMS) setup time

62 JTEST1 (TMS) hold time

63 JTEST2 (TDI) setup time

64 JTEST2 (TDI) hold time

65 JTEST3 (TDO) valid delay

Limit Values

Unit

min.

max.

166

inf

–

80

–

–

80

–

–

15

–

–

10

–

–

15

–

–

15

–

–

30

–

–

User’s Manual

241

01.2000

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